M69030 Asiliant Technologies, M69030 Datasheet - Page 140

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-38
CR41
read/write at I/O address 3B5h/3D5h with 3B4h/3D4h set to index 41
shadowed for pipelines A and B
7-4
3-0
CR70
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 70h
shadowed for pipelines A and B
7
6-0
`efmp
A
B
A
B
Interlace
Interlace

Enable
Enable
Reserved
Offset Bits 11-8
Interlace Enable
CRT Half-Line Value
69030 Databook
7
7
Extended Span Register
Interlace Control Register
Whenever this register is written to, these bits should be set to 0.
The offset is an 8-bit or 12-bit value describing the number of words or doublewords of
frame buffer memory occupied by each horizontal row of characters. Whether this value is
interpreted as the number of words or doublewords is determined by the settings of the bits
in the Clocking Mode Register (SR01).
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the offset
is described with an 8-bit value, all the bits of which are provided by the Offset Register
(CR13).
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the offset is
described with a 12-bit value. The four most significant bits of this value are provided by
bits 3-0 of this register, and the eight least significant bits are provided by the Offset
Register (CR13).
This 8-bit or 12-bit value should be programmed to be equal to either the number of words
or doublewords (depending on the setting of the bits in the Clocking Mode Register, SR01)
of frame buffer memory that is occupied by each horizontal row of characters.
0: Selects non-interlaced CRT output. This is the default after reset.
1: Selects interlaced CRT output.
When interlaced CRT output has been selected, these 7 bits specify the position along the
length of a scan line at which the half-line vertical sync pulse occurs for the odd frame. This
half-line vertical sync pulse begins at a position between two horizontal sync pulses on the
last scanline, rather than coincident with the beginning of a horizontal sync pulse at the end
of a scanline.
6
6
Reserved
Reserved
5
5
CRT Controller Registers
4
4
CRT Half-Line Value
CRT Half-Line Value
3
3
Offset Bits 11-8
Offset Bits 11-8
2
2
Revision 1.3 11/24/99
1
1
0
0