M69030 Asiliant Technologies, M69030 Datasheet - Page 61

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 5-4:
Memory Space Register Shadowing
When the graphics controller is used in dual-pipe mosaic mode with newer operating systems, it is expected
that each pipeline will be controlled by its own incarnation of a 2D driver, and that each driver will need to
be given its own memory address range through which it controls the registers belonging to its pipeline. To
accommodate this, a memory-map address mode is provided wherein one pipeline has its registers mapped
within memory offsets 400000 through 7FFFFF while the registers of the other pipeline are mapped to
memory offsets C00000 through FFFFFF. The essential idea is to allow each incarnation of the 2D driver
to control the pipeline corresponding to it, while staying out of the way of the other incarnation.
However, when the graphics controller is used in dual-pipe simultaneous mode, it is generally expected that
only one incarnation of the 2D driver will be loaded, and that it will be the same driver that is normally used
to control all single-pipeline modes. Such a driver may not be written to make duplicate reads and writes to
two pipelines in order to get the same thing going on both, and so, as in the case of the I/O space, a
“shadowing” scheme is implemented in the memory space, such that the one 2D driver may write to the
same registers in both pipelines simultaneously in single write operations. This shadowing scheme is under
the control of the Memory Space Shadowing Register (MSS). MSS provides a means of temporarily
choosing one or the other of the two sets of registers to be made writable for those few occasional situations
where a register belonging to one pipeline must be set to something different from the same register
belonging to the other pipeline. MSS also provides the mechanism by which one or the other of the two sets
of registers is selected for read operations, since it is not possible to read from both sets simultaneously.
Video Playback Engine Register Cross-Sharing
This graphics controller has two video playback engines, numbers 1 and 2, to answer both the need to show
the same playback image through both pipes in dual-pipe simultaneous mode, and the need to show two
different images for video conferences in either dual-pipe mosaic mode or the single-pipe modes. To do all
of these things, the two video playback engines are “reassignable” -- i.e., each playback engine can be set
to be used with either pipe.
Through I/O space shadowing, parallel sets of MR register locations, specifically MR1E through MR42, are
created for each pipeline which permit one playback engine to be used with each pipe. However, to use
both playback engines simultaneously with either one or the other of the two pipes, a second set of
shadowed MR register locations (MR9E through MRC2) has been allocated to allow access to a second
playback engine.
The following figure shows this interplay of registers and register locations with three of the main elements
of the multimedia portion of the graphics controller: a video data capture engine and two video playback
engines.
`efmp
bits 7-6 and 4-0 of MR9E

69030 Databook
(playback engine 2)
(playback engine 2)
MR9F-MRC2
MR43-MR44
I/O Space Register Shadowing (Continued)
I/O and Memory Address Maps
BR00 to BR0F
ER00 to ER0F
bit 5 of MR9E
bits 7-6 and 4-0 of MR9E
(playback engine 1)
(playback engine 1)
MR9F-MRC2
MR43-MR44
Revision 1.3 11/24/99
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