M69030 Asiliant Technologies, M69030 Datasheet - Page 334

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

18-2
ER00
doubleword-writable, byte/word/doubleword-readable at memory offsets 0x400600 and 0xC00600
shared by both pipelines A and B
31
30
29-19
18
17-15
14
13-7
6
5-0
`efmp
A
&
B
A
&
B
BBLT
Rsvd
Idle
(0)
(0)
31
15

BitBLT Engine Idle Interrupt Output Enable
BitBLT Engine Command Queue Low Interrupt Pending
Reserved
Pipeline B Vertical Blanking Period Interrupt Output Enable
Reserved
Pipeline A Vertical Blanking Period Interrupt Output Enable
Reserved
Video Capture Vertical Sync Interrupt Output Enable
Reserved
69030 Databook
Queue
Pipe A
V Blnk
BBLT
(0)
(0)
30
14
Central Interrupt Control Register
0: No hardware interrupt is output to the host when the BitBLT engine becomes idle after
performing a BitBLT operation.
1: Causes a hardware interrupt to be output to the host when the BitBLT engine becomes
idle after performing a BitBLT operation.
0: Since this bit was last cleared, no interrupt has been sourced as a result of the command
queue used by the BitBLT engine going below the low watermark.
1: An interrupt was sourced as a result of the command queue used by the BitBLT engine
going below the low watermark. Writing the value of 1 to this bit will clear it to 0 (writing the
value of 0 to this bit has no effect and will be ignored).
These bits always return the value of 0 when read.
0: No hardware interrupt is output to the host when the last pixel of the last scan line within
the active display area is drawn on pipeline B.
1: Causes a hardware interrupt to be output to the host when the last pixel of the last scan
line within the active display area is drawn on pipeline B.
This bit always return the value of 0 when read.
These bits always return the value of 0 when read.
0: No hardware interrupt is output to the host when the last pixel of the last scan line within
the active display area has been drawn on pipeline A.
1: Causes a hardware interrupt to be output to the host when the last pixel of the last scan
line within the active display area has been drawn on pipeline A.
These bits always return the value of 0 when read.
0: No hardware interrupt is output to the host at the start of each vertical sync pulse from
the acquisition data source.
1: Causes a hardware interrupt to be output to the host at the start of each vertical sync
pulse from the acquisition data source.
These bits always return the value of 0 when read.
29
13
28
12
Memory-Mapped Wide Extension Registers
27
11
(00:0000:0)
Reserved
26
10
(00:0000:0000:0)
25
9
Reserved
24
8
23
7
VSync
V Cap
(0)
22
6
21
5
20
4
19
Reserved
(00:0000)
3
Revision 1.3 11/24/99
Pipe B
V Blnk
(0)
18
2
Reserved
17
1
(00)
16
0