PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet
PI7C9X111SLBFDE
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PI7C9X111SL PCI Express-to-PCI Reversible Bridge Revision 1.5 ST 3545 North 1 Street, San Jose, CA 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com ...
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... Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. ...
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... This document describes the functionalities of PI7C9X111SL (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X111SL. Pericom Semiconductor - Confidential DESCRIPTION Released Version 1.0 Datasheets Revised General Feature to reflect I-temp ...
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... SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 28 6.3.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 29 6.3.15 I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 29 6.3.16 I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 29 Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 46 6.3.66 CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 46 6.3.67 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 46 6.3.68 CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 47 Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 61 6.3.118 RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 61 6.3.119 VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 61 6.3.120 VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 61 Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... BOUNDARY SCAN REGISTER.......................................................................................... 73 13.5 JTAG BOUNDARY SCAN REGISTER ORDER................................................................. 73 14 POWER MANAGEMENT.......................................................................................................... 73 15 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................ 75 15.1 ABSOLUTE MAXIMUM RATINGS ................................................................................... 75 15.2 DC SPECIFICATIONS .......................................................................................................... 75 15.3 AC SPECIFICATIONS .......................................................................................................... 76 16 PACKAGE INFORMATION ..................................................................................................... 77 17 ORDERING INFORMATION ................................................................................................... 78 Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... PCI ABLE INTERRUPT TO T 13-1 I ABLE NSTRUCTION REGISTER CODES T 13-2 JTAG ID ABLE DEVICE T 15-1 A ABLE BSOLUTE MAXIMUM RATINGS T 15-2 DC ABLE ELECTRICAL CHARACTERISTICS T 15-3 PCI ABLE BUS TIMING PARAMETERS Pericom Semiconductor - Confidential ............................................................................................... 10 OPOLOGY M ..................................................................................................... 18 ODE ....................................................................................................... 19 ODE ........................................................................................ 76 ............................................................................................. 77 M (00 – FF )....................................................................... APABILITY EGISTER ............................................................................................ 64 TRAPPING ...
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... This page intentionally left blank. Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... ASPM support • Beacon support • CRC (16-bit), LCRC (32-bit) • ECRC and advanced error reporting • PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing Pericom Semiconductor - Confidential PCI Express Port PI7C9X111SL PCI 32bit / 66MHz Bus PCI PCI PCI Device ...
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... EEPROM (I2C) Interface • SM Bus Interface • Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support • Power consumption less than 0.45 Watt in typical condition • Industrial temperature range (-40C ~ +85C) Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... CBE_L[3:0] 115, 102, 90, 79 PAR 93 FRAME_L 66 Pericom Semiconductor - Confidential TYPE DESCRIPTION I Reference Clock Inputs: Connect to external 100MHz differential clock. These signals require AC coupled with 0.1uF capacitors. I PCI Express data inputs: Differential data receiver input signals O ...
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... INTB_L 47 INTC_L 62 INTD_L 61 Pericom Semiconductor - Confidential TYPE DESCRIPTION B IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase not de-asserted until the end of the data phase. Before tri-stated driven to a de- asserted state for one cycle ...
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... NAME PIN ASSIGNMENT CLKIN 48 Pericom Semiconductor - Confidential TYPE DESCRIPTION I PCI Clock Input: PCI Clock Input Signal connects to an external clock source. The PCI Clock Outputs CLKOUT [3:0] pins are derived from CLKIN Input. Page PI7C9X111SL PCIe-to-PCI Reversible Bridge Feb, 2010, Revision 1.5 ...
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... VDDCAUX 5 VD33 33, 53, 60, 70, 81, 91, 101, 111, 122 Pericom Semiconductor - Confidential TYPE DESCRIPTION I Mode Select 0: Mode Selection Pin to select EEPROM or SM Bus. TM0=0 for EEPROM (I2C) support and TM0=1 for SM Bus support. TM0 is also a strapping pin. See table 3-1 mode selection and 3-2 for strapping control. ...
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... VSS 26 TM1 27 TMS 28 TCK 29 TDI 30 TRST_L 31 REVRSB 32 TDO 3 MODE SELECTION AND PIN STRAPPING Pericom Semiconductor - Confidential TYPE DESCRIPTION P Auxiliary I/O Supply Voltage for PCI interface: Connect to the 3.3V Power Supply. P Ground: Connect to Ground. PIN NAME PIN 33 VD33 65 34 VSS 66 35 REQ_L[0] ...
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... If TM1 is strapped to high, PI7C9X111SL uses TM0, REVRSB as the strapping pins at the PCIe PERST# de- assertion transition in forward bridge mode or PCI RESET# de-assertion transition in reverse bridge mode. TM1 Strapped TM0 Strapped Pericom Semiconductor - Confidential REVRSB Functional Mode X EEPROM (I2C) support X SM Bus support ...
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... PCI Express Interface capability. PI7C9X111SL provides a solution to convert existing PCI based designs to adapt quickly into PCI Express base platforms. Existing PCI based applications will not have to undergo a complete re-architecture in order to interface to PCI Express technology. Pericom Semiconductor - Confidential Host Processor System ...
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... Figure 4-2 Reverse Bridge Mode System Memory PI7C9X111SL Pericom Semiconductor - Confidential Host Processor Host PCI Chipset PCI 32bit / 66MHz Fibre Fast Channel Ethernet x1 link Page PI7C9X111SL PCIe-to-PCI Reversible Bridge SCSI HDD Feb, 2010, Revision 1.5 ...
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... Express-to-PCI). If configuration, IO and message packets have traffic class other than TC0, PI7C9X111SL will treat them as malformed packets. PI7C9X111SL maps all downstream memory packets from PCI Express to PCI transactions regardless the virtual Isochronous operation is enabled or not. Pericom Semiconductor - Confidential FMT [0] TLP Format ...
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... Memory Base Register 23h – 22h Memory Limit Register 25h – 24h Prefetchable Memory Base Register 27h – 26h Prefetchable Memory Limit Register 2Bh – 28h Prefetchable Memory Pericom Semiconductor - Confidential EEPROM SM Bus (I2C) Access Access Yes1 Yes2 Yes1 Yes2 Yes Yes ...
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... Reserved 7Fh Reserved 83h – 80h PCI-X Capability 87h – 84h PCI-X Bridge Status 8Bh – 88h Upstream Split Transaction 8Fh – 8Ch Downstream Split Pericom Semiconductor - Confidential EEPROM SM Bus (I2C) Access Access Yes Yes Yes Yes Yes Yes Yes ...
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... PI7C9X111SL also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space. The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting (ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h). Pericom Semiconductor - Confidential EEPROM SM Bus (I2C) ...
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... Acknowledge Latency Timer 4FFh – 314h Reserved 503h – 500h Reserved 504h Reserved 50Fh – 505h Reserved 510h Reserved FFFh – 514h Reserved Note 5: Read access only. Pericom Semiconductor - Confidential EEPROM SM Bus (I2C) Access Access Yes Yes2 No Yes Yes Yes No Yes No ...
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... Bus Master Enable 3 Special Cycle Enable 4 Memory Write and Invalidate Enable 5 VGA Palette Snoop Enable Pericom Semiconductor - Confidential Descriptions Read Only Read Only and Sticky Read/Write Read/Write “1” to clear Read/Write and Sticky Read/Write “1” to clear and Sticky TYPE DESCRIPTION RO Identifies Pericom as the vendor of this device ...
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... Reserved 23 Fast Back-to-Back Capable 24 Master Data Parity Error Detected Pericom Semiconductor - Confidential TYPE DESCRIPTION RW 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and ...
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... CLASS CODE REGISTER – OFFSET 08h BIT FUNCTION 15:8 Programming Interface 23:16 Sub-Class Code 31:24 Base Class Code Pericom Semiconductor - Confidential TYPE DESCRIPTION RO These bits apply to reverse bridge only. 00: fast DEVSEL_L decoding 01: medium DEVSEL_L decoding 10: slow DEVSEL_L decoding 11: reserved Reset to 00 when forward bridge or 01 when reverse bridge. ...
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... Primary Bus Number 6.3.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTION 15:8 Secondary Bus Number 6.3.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Bit [1:0] not supported Reset Cache line size = 4 double words Reset to 0 ...
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... BIT FUNCTION 20:16 Reserved 21 66MHz Capable 22 Reserved 23 Fast Back-to-Back Capable 24 Master Data Parity Error Detected Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Reset to 00h TYPE DESCRIPTION RW / Secondary latency timer in PCI bus RO FORWARD BRIDGE – RW with reset to 00h in PCI mode REVERSE BRIDGE – RO with reset to 00h ...
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... FUNCTION 19:16 Reserved 31:20 Memory Limit 6.3.20 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RO These bits apply to forward bridge only. 01: medium DEVSEL_L decoding Reset to 01 when forward mode or 00 when reverse mode. RWC FORWARD BRIDGE – ...
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... Prefetchable Memory Base 6.3.21 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h BIT FUNCTION 19:16 64-bit Addressing Support 31:20 Prefetchable Memory Limit Pericom Semiconductor - Confidential TYPE DESCRIPTION RO 0001: Indicates PI7C9X111SL supports 64-bit addressing Reset to 0001 RW Prefetchable Memory Base (00000000_80000000h) Reset to 800h ...
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... EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h BIT FUNCTION 31:0 Expansion ROM Base Address 6.3.28 INTERRUPT LINE REGISTER – OFFSET 3Ch BIT FUNCTION 7:0 Interrupt Line Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Bit [63:32] of prefetchable base Reset to 00000000h TYPE DESCRIPTION RW Bit [63:32] of prefetchable limit Reset to 00000000h ...
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... ISA Enable 19 VGA Enable 20 VGA 16-bit Decode 21 Master Abort Mode 22 Secondary Interface Reset 23 Fast Back-to-Back Enable Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Designates interrupt pin INTA_L, is used Reset to 01h TYPE DESCRIPTION RW 0: Ignore parity errors on the secondary 1: Enable parity error detection on secondary FORWARD BRIDGE – ...
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... Dynamic Control Disable 2 Completion Data Prediction Control 3 CFG Type0-to-Type1 conversion Enable 5:4 PCI Read Multiple Prefetch Mode Pericom Semiconductor - Confidential TYPE DESCRIPTION RW 0: Primary discard timer counts 2 1: Primary discard timer counts 2 FORWARD BRIDGE – Bit is RO and ignored by the PI7C9X111SL Reset ...
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... CHIP CONTROL 0 REGISTER – OFFSET 40h BIT FUNCTION 15 Flow Control Update Control Pericom Semiconductor - Confidential TYPE DESCRIPTION RW 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the ...
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... Traffic Class Used For Isochronous Traffic 30 Power Saving mode enable 31 Primary Configuration Access Lockout Pericom Semiconductor - Confidential TYPE DESCRIPTION RWC 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 ...
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... BIT FUNCTION 9 External Arbiter Bit 10 Broken Master Timeout Enable 11 Broken Master Refresh Enable 19:12 Arbiter Fairness Counter Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Reset to 00000000h TYPE DESCRIPTION RW 0: Disable arbitration for internal PI7C9X111SL request 1: Enable arbitration for internal PI7C9X111SL request Reset Disable arbitration for master 1 ...
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... MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h BIT FUNCTION 31:0 Memory Readsmart Base Upper 32-bit register 1 Pericom Semiconductor - Confidential TYPE DESCRIPTION RW 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting ...
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... FUNCTION 31:0 Memory Readsmart Range Size register 2 6.3.44 EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RW define the size of the range 1, maximum 4G byte with granuity of 2 bytes RW Memory Readsmart Range Control register 0: any PCI memory read with address falling in the range are not allowed to use Readsmart mode ...
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... Transmitter Termination Control 15:14 Receiver Termination Control 29:16 Reserved 6.3.45 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RW 00: 20mA 01: 10mA 10: 28mA 11: Reserved Reset 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1 ...
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... Control 6 EEPROM Autoload Control 7 Fast EEPROM Autoload Control 8 EEPROM Autoload Status 15:9 EEPROM Word Address 31:16 EEPROM Data Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 10h TYPE DESCRIPTION RW This bit will be reset to 0 after the EEPROM operation is finished ...
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... PCI-X SECONDARY STATUS REGISTER – OFFSET 80h BIT FUNCTION 16 64-bit Device on Secondary Bus Interface 17 133MHz Capable 18 Split Completion Discarded 19 Unexpected Split Completion 20 Split Completion Overrun 21 Split Request Delayed Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Reset to 000h RW Reset Reset Reset Reset Reset to 0h TYPE DESCRIPTION ...
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... Split Completion Overrun 21 Split Request Delayed 31:22 Reserved 6.3.55 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h Pericom Semiconductor - Confidential TYPE DESCRIPTION RO These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7 ...
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... Next Pointer 6.3.59 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h BIT FUNCTION 18:16 Version Number Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus ...
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... Data Select 14:13 Data Scale 15 PME Status 6.3.61 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RO PME clock is not required for PME_L generation Reset Reset DSI – no special initialization of this function beyond the standard PCI ...
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... CHASSIS NUMBER REGISTER – OFFSET A0h BIT FUNCTION 31:24 Chassis Number 6.3.67 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h BIT FUNCTION 1:0 S_CLKOUT0 Enable Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Reset to 000000 not support for D3hot Reset PCI Bus Power/Clock Disabled ...
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... CAPABILITY ID REGISTER – OFFSET A8h BIT FUNCTION 7:0 Capability ID 6.3.69 NEXT POINTER REGISTER – OFFSET A8h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RW S_CLKOUT (Slot 1) Enable for forward bridge mode only 00: enable S_CLKOUT1 01: enable S_CLKOUT1 10: enable S_CLKOUT1 11: disable S_CLKOUT1 and driven LOW ...
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... Device / Port Type 24 Slot Implemented 29:25 Interrupt Message Number 31:30 Reserved 6.3.76 DEVICE CAPABILITY REGISTER – OFFSET B4h Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Next item pointer (point to PCI Express Capability by default but can be programmed to A0h if Slot Identification Capability is enabled) Reset to B0h TYPE ...
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... Reserved 25:18 Captured Slot Power Limit Value 27:26 Captured Slot Power Limit Scale 31:28 Reserved Pericom Semiconductor - Confidential TYPE DESCRIPTION RO 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved ...
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... Correctable Error Detected 17 Non-Fatal Error Detected 18 Fatal Error Detected 19 Unsupported Request Detected 20 AUX Power Detected 21 Transaction Pending 31:22 Reserved Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Reset Reset Reset Reset Relaxed Ordering disabled Reset This field sets the maximum TLP payload size for the PI7C9X111SL ...
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... Common Clock Configuration 7 Extended Sync 15:8 Reserved 6.3.81 LINK STATUS REGISTER – OFFSET C0h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset Indicates the maximum width of the Express link (x1 at reset) ...
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... Physical Slot Number 6.3.83 SLOT CONTROL REGISTER – OFFSET C8h BIT FUNCTION 0 Attention Button Present Enable 1 Power Fault Detected Enable Pericom Semiconductor - Confidential TYPE DESCRIPTION RO This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset 000000: reserved 000001: x1 ...
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... L1 Lifetime Timer 6.3.87 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h BIT FUNCTION 7:0 CDR Recovery Time (in the number of FTS order sets) 14:8 L0’s Exit to L0 Latency 15 Reserved 22:16 L1 Exit to L0 Latency 23 Reserved Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Reset Reset Reset Reset Reset Reset to 0 ...
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... Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... Reserved 23:18 VPD Address for Read/Write Cycle 30:24 Reserved 31 VPD Operation 6.3.92 VPD DATA REGISTER – OFFSET DCh BIT FUNCTION 31:0 VPD Data Pericom Semiconductor - Confidential TYPE DESCRIPTION RW L0 enter L1 waiting period counter =d0: 128ms =d1: 129ms . . =d127: 256ms =d128: 0ms =d129: 1ms . ...
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... Reserved 31:2 System Specified Message Address 6.3.98 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h BIT FUNCTION 31:0 System Specified Message Upper Address Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Reset to 05h TYPE DESCRIPTION RO Next pointer (00h indicates the end of capabilities) Reset to 00h TYPE ...
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... UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h BIT FUNCTION 0 Training Error Mast 3:1 Reserved 4 Data Link Protocol Error Mask 11:5 Reserved 12 Poisoned TLP Mask 13 Flow Control Protocol Error Mask Pericom Semiconductor - Confidential TYPE DESCRIPTION RW Reset Reset to 0 TYPE DESCRIPTION RO Reset to 0001h TYPE DESCRIPTION RO Reset to 1h TYPE DESCRIPTION ...
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... Reserved 6 Bad TLP Mask 7 Bad DLLP Mask 8 REPLAY_NUM Rollover Mask 11:9 Reserved 12 Replay Timer Timeout Mask 31:13 Reserved Pericom Semiconductor - Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 ...
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... Target Abort on Split Completion Status 1 Master Abort on Split Completion Status 2 Received Target Abort Status 3 Received Master Abort Status 4 Reserved 5 Unexpected Split Completion Error Status Pericom Semiconductor - Confidential TYPE DESCRIPTION ROS Reset Reset to 1 RWS Reset Reset to 1 RWS Reset Reset to 0 TYPE ...
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... Target Abort on Split Completion Severity 1 Master Abort on Split Completion Severity 2 Received Target Abort Severity 3 Received Master Abort Severity 4 Reserved Pericom Semiconductor - Confidential TYPE DESCRIPTION RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 ...
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... Transaction Address 6.3.118 RESERVED REGISTER – OFFSET 14Ch 6.3.119 VC CAPABILITY ID REGISTER – OFFSET 150h BIT FUNCTION 15:0 VC Capability ID 6.3.120 VC CAPABILITY VERSION REGISTER – OFFSET 150h Pericom Semiconductor - Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 1 RWS Reset to 0 RWS ...
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... Reject Snoop Transactions 22:16 Maximum Time Slots 23 Reserved 31:24 Port Arbitration Table Offset 6.3.127 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h BIT FUNCTION Pericom Semiconductor - Confidential TYPE DESCRIPTION RO Reset to 1h TYPE DESCRIPTION RO Next capability offset – the end of capabilities Reset to 0 TYPE ...
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... Replay Timer 12 Replay Timer Enable 15:13 Reserved 29:16 Acknowledge Latency Timer 30 Acknowledge Latency Timer Enable 31 Reserved 6.3.133 RESERVED REGISTERS – OFFSET 314h – FFCh Pericom Semiconductor - Confidential TYPE DESCRIPTION RO For TC0 Reset For TC7 to TC1 Reset to 7Fh RO Reset Reset Reset to 0 ...
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... Read Word protocol (PEC Disabled Slave Address[7:1] + 0(Wr 0000_1000 + A + Bus Number[7: Device/Function + Slave Address[7:1] + 0(Wr 0000_1000 + A + Reg Number[7: Reg Number[15: Slave Address[7:1] + 0(Wr 0000_1000 + Slave Address[7:1] + 1(Rd Data[7: Data[15: Where Bus number and device/Function filed have to be 0x00 Pericom Semiconductor - Confidential SM Bus device GPIO [3] ...
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... Internal feedback o External feedback o • External clock source, and internal clock buffering. Internal feedback o External feedback o • External clock source, and external clock buffering. Pericom Semiconductor - Confidential PCI Clock 33MHz 66MHz 25MHz 50MHz Page PI7C9X111SL PCIe-to-PCI Reversible Bridge Feb, 2010, Revision 1.5 ...
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... External Feedback: PI7C9X111SL Clock CLKIN Generator Topology of external clock source and internal clock buffering: 1. Internal Feedback: PI7C9X111SL Clock CLKIN source 2. External Feedback: Pericom Semiconductor - Confidential CLKOUT0 PCI Device CLKOUT1 PCI Device CLKOUT2 PCI Device CLKOUT3 PCI Device CLKOUT0 Note: Feedback source could be ...
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... In this configuration, user simply connects the external clock from the clock buffers to CLKOUT0. And user needs to make sure the clock is preset (toggling) before the fundamental reset de-asserted (e.g. PERST_L when forward mode, and RESET_L when reverse mode). 9 INTERRUPTS Pericom Semiconductor - Confidential PI7C9X111SL Clock Generator External ...
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... SYSTEM MANAGEMENT BUS PI7C9X111SL supports SM bus protocol if TM1=0 and TM0=1. In addition, SMBCLK (pin 3) and SMBDAT (pin 4) are utilized as the clock and data pins respectively for the SM bus. Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge PCI Interrupts (to host controller) INTA ...
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... A4-A7h 26-29h A8-ABh 2A-2Dh AC-AFh Pericom Semiconductor - Confidential Description EEPROM signature: Autoload will only proceed if it reads a value of 1516h on the first word loaded. Region Enable: Enables or disables certain regions of PCI configuration space from being loaded from the EEPROM. bit 0: reserved ...
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... CC-CFh 2C-2Fh D0-D3h 30-33h D4-D5h D6-D7h 3E-3Fh D8-FFh 11 HOT PLUG OPERATION Pericom Semiconductor - Confidential Description PCI Express Capabilities Device Capabilities Link Capabilities Slot Capabilities XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 VPD Capability MSI Capability Advance Error Reporting Capability ...
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... DL_DOWN Reset: If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status. PI7C9X111SL discards all transactions and returns all logic and registers to initial state except the sticky registers. Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 ...
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... IDCODE 01100 BYPASS 11111 INT_SCAN 00010 MEM_BIST 01010 13.2 BYPASS REGISTER Pericom Semiconductor - Confidential Register Selected Operation Boundary Scan Drives / receives off-chip test data Boundary Scan Samples inputs / pre-loads outputs Bypass Tri-states output and I/O pins except TDO pin Bypass ...
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... PME_L in forward bridge mode. PI7C9X111SL converts PME_L signal information to power management messages to the upstream switches or root complex. In reverse bridge mode, PI7C9X111SL converts the power management event messages from PCIe devices to the PME_L signal and continues to request power management state change to the host bridge. Pericom Semiconductor - Confidential Value Description 01h ...
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... PI7C9X111SL also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X111SL supports beacon generation but does not support WAKE# signal during power management. Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 PI7C9X111SL ...
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... By the same token, VD33/VDDC and VAUX/VDDCAUX need to be separated for auxiliary power management support. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X111SL is less than 0.45 watt. Pericom Semiconductor - Confidential o -65 o -40 -0 ...
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... Point-to-point signals are REQ_L [7:0], GNT_L [7:0], LOO, and ENUM_L. Bused signals are AD, CBE, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, LOCK_L, STOP_L and IDSEL. 4. REQ_L signals have a setup of 10ns and GNT_L signals have a setup of 12ns. Figure 15-1 PCI signal timing conditions Pericom Semiconductor - Confidential 66 MHz MIN 1,2,3 ...
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... Pericom highly recommends implementing this exposed ground pad on any customer boards. The following are the package information and mechanical dimension: Figure 16-1 Package outline drawing Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge Page Feb, 2010, Revision 1.5 ...
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... ORDERING INFORMATION PART NUMBER PIN – PACKAGE PI7C9X111SLBFDE 128 – LQFP (Exposed ground pad) NOTES: Pericom Semiconductor - Confidential PCIe-to-PCI Reversible Bridge PB-FREE & GREEN YES Page Feb, 2010, Revision 1.5 PI7C9X111SL TEMPERATURE RANGE -40C TO +85C ...