PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 68

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

10
10.1 EEPROM (I2C) INTERFACE
10.2 SYSTEM MANAGEMENT BUS
PI7C9X111SL supports interrupt message packets on PCIe side. PI7C9X111SL supports PCI interrupt (INTA, B,
C, D) pins or MSI (Message Signaled Interrupts) on PCI side. PCI interrupts and MSI are mutually exclusive. In
order words, if MSI is enabled, PCI interrupts will be disabled. PI7C9X111SL support 64-bit addressing MSI.
In reverse bridge mode, PI7C9X111SL maps the interrupt message packets to PCI interrupt pins or MSI if MSI is
enable (see configuration register bit [16] of Offset F0h).
In forward bridge mode, PI7C9X111SL maps the PCI interrupts pins or MSI if enable on PCI side to interrupt
message packets on PCIe side.
There are eight interrupt message packets. They are Assert_INTA, Assert_INTB, Assert_INTC, Assert_INTD,
Deassert_INTA, Deassert_INTB, Deassert_INTC, and Deassert_INTD. These eight interrupt messages are mapped
to the four PCI interrupts (INTA, INTB, INTC, and INTD). See Table 9-1 for interrupt mapping information in
reverse bridge mode. PI7C9X111SL tracks the PCI interrupt (INTA, INTB, INTC, and INTD) pins and maps them
to the eight interrupt messages. See Table 9-2 for interrupt mapping information in forward bridge mode.
Table 9-1 PCIe interrupt message to PCI interrupt mapping in reverse bridge mode
PI7C9X111SL supports EEPROM interface through I2C bus. In EEPROM interface, pin 3 is the EEPROM clock
(SCL) and pin 4 is the EEPROM data (SDL). TM1 and TM0 are strapped accordingly to select EEPROM interface
or System Management Bus. EEPROM (I2C) interface is enabled with TM1=0 and TM0=0. When EEPROM
interface is selected , SCL is an output. SCL is the I2C bus clock to the I2C device. In addition, SDL is a bi-
directional signal for sending and receiving data.
PI7C9X111SL supports SM bus protocol if TM1=0 and TM0=1. In addition, SMBCLK (pin 3) and SMBDAT (pin
4) are utilized as the clock and data pins respectively for the SM bus.
Pericom Semiconductor - Confidential
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS
PCIe Interrupt messages (from sources of interrupt)
INTA message
INTB message
INTC message
INTD message
PCI Interrupts (from sources of interrupts)
INTA
INTB
INTC
INTD
Table 9-2 PCI interrupt to PCIe interrupt message mapping in forward bridge mode
Page 68 of 78
PCI Interrupts (to host controller)
INTA
INTB
INTC
INTD
PCIe Interrupt message packets (to host controller)
INTA message
INTB message
INTC message
INTD message
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL