PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 35

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.32 CHIP CONTROL 0 REGISTER – OFFSET 40h
Pericom Semiconductor - Confidential
BIT
7:6
9:8
10
11
14:12
BIT
15
FUNCTION
PCI Read Line Prefetch
Mode
PCI Read Prefetch Mode
PCI Special Delayed Read
Mode Enable
Optional Malformed Packet
checking Enable
Maximum Memory Read
Byte Count
FUNCTION
Flow Control Update
Control
TYPE
TYPE
RW
RW
RW
RW
RW
RW
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DESCRIPTION
00: Once cache line prefetch if memory read address is in prefetchable range
at PCI interface
01: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X111SL will keep remaining data after it is disconnected by an
external master during burst read with read line command, until discard timer
expires
10: Full prefetch if memory read line address is in prefetchable range at PCI
interface
11: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X111SL will keep remaining data after the read line is terminated
either by an external master or by the PI7C9X111SL, until the discard timer
expires
Reset to 00
00: One cache line prefetch if memory read address is in prefetchable range
at PCI interface
01: Reserved
10: Full prefetch if memory read address is in prefetchable range at PCI
interface
11: Disconnect on the first DWORD
Reset to 00
0: Retry any master at PCI bus that repeats its transaction with command
code changes.
1: Allows any master at PCI bus to change memory command code (MR,
MRL, MRM) after it has received a retry. The PI7C9X111SL will complete
the memory read transaction and return data back to the master if the address
and byte enables are the same.
Reset to 0
0: Optional Malformed Packet checking is disabled
1: Optional Malformed Packet checking is enabled
Reset to 0
Maximum byte count is used by the PI7C9X111SL when generating memory
read requests on the PCIe link in response to a memory read initiated on the
PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to “full prefetch”.
000: 512 bytes (default)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
101: 2048 bytes
110: 4096 bytes
111: 512 bytes
Reset to 000
DESCRIPTION
0: Flow control is updated for every two credits available
1: Flow control is updated for every on credit available
Reset to 0
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL