PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 5

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

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Pericom Semiconductor - Confidential
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 29
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 30
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 30
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h......................................................... 30
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h........................................................ 31
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 32
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch............................................... 32
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h......................................................................... 32
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 32
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 32
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 32
INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................... 32
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 33
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 33
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 34
CHIP CONTROL 0 REGISTER – OFFSET 40h................................................................................... 35
RESERVED REGISTER – OFFSET 44h............................................................................................... 37
ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 37
ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 37
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 38
RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 38
MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 38
MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 38
MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 39
MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 39
MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 39
MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 39
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 39
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 40
RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 41
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 41
RESERVED REGISTER – OFFSET 74h............................................................................................... 42
GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 42
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 42
PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 42
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 42
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h.................................................................. 42
PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.......................................................................... 43
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 43
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 44
POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 44
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 44
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 44
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 45
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 45
RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 46
CAPABILITY ID REGISTER – OFFSET A0h....................................................................................... 46
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 46
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 46
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 46
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 46
CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 47
Page 5 of 78
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL