PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 51

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.79 LINK CAPABILITY REGISTER – OFFSET BCh
6.3.80 LINK CONTROL REGISTER – OFFSET C0h
6.3.81 LINK STATUS REGISTER – OFFSET C0h
Pericom Semiconductor - Confidential
BIT
3:0
9:4
11:10
14:12
17:15
23:18
31:24
BIT
1:0
2
3
4
5
6
7
15:8
BIT
FUNCTION
Maximum Link Speed
Maximum Link Width
ASPM Support
L0’s Exit Latency
L1’s Exit Latency
Reserved
Port Number
FUNCTION
ASPM Control
Reserved
Read Completion Boundary
(RCB)
Link Disable
Retrain Link
Common Clock
Configuration
Extended Sync
Reserved
FUNCTION
TYPE
TYPE
TYPE
RO /
RO /
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Indicates the maximum speed of the Express link
0001: 2.5Gb/s link
Reset to 1
Indicates the maximum width of the Express link (x1 at reset)
000000: reserved
000001: x1
000010: x2
000100: x4
001000: x8
001100: x12
010000: x16
100000: x32
Reset to 000001
This field indicates the level of Active State Power Management Support
00: reserved
01: L0’s entry supported
10: reserved
11: L0’s and L1’s supported
Reset to 11
Reset to 3h
Reset to 0/6h
Reset to 0/1h
Reset to 00h
DESCRIPTION
This field controls the level of ASPM supported on the Express link
00: disabled
01: L0’s entry enabled
10: L1’s entry enabled
11: L0’s and L1’s entry enabled
Reset to 00
Reset to 0
Read completion boundary not supported
Reset to 0
RO for Forward Bridge
Reset to 0
RO for Forward Bridge
Reset to 0
Reset to 0
Reset to 0
Reset to 00h
DESCRIPTION
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL