PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 42

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.48 RESERVED REGISTER – OFFSET 74h
6.3.49 GPIO DATA AND CONTROL REGISTER – OFFSET 78h
6.3.50 RESERVED REGISTER – OFFSET 7Ch
6.3.51 PCI-X CAPABILITY ID REGISTER – OFFSET 80h
6.3.52 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h
6.3.53 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h
Pericom Semiconductor - Confidential
BIT
11:0
15:12
19:16
23:20
27:24
31:28
BIT
7:0
BIT
15:8
BIT
16
17
18
19
20
21
FUNCTION
Reserved
GPIO Output Write-1-to-
Clear
GPIO Output Write-1-to-Set
GPIO Output Enable Write-
1-to-Clear
GPIO Output Enable Write-
1-to-Set
GPIO Input Data Register
FUNCTION
PCI-X Capability ID
FUNCTION
Next Capability Pointer
FUNCTION
64-bit Device on Secondary
Bus Interface
133MHz Capable
Split Completion Discarded
Unexpected Split
Completion
Split Completion Overrun
Split Request Delayed
RWC/RO
TYPE
TYPE
TYPE
TYPE
RWC
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 000h
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
DESCRIPTION
PCI-X Capability ID
Reset to 07h
DESCRIPTION
Point to power management
Reset to 90h
DESCRIPTION
64-bit not supported
Reset to 0
133MHz capable on secondary interface. this bit is always RO.
Split Completion Discarded this bit is always RO.
Reset to 0
requeste
00h, and function number 0 on the bridge secondary interface. this bit is RO
for forward bridge.
Reset to 0
This bit is always RO.
Reset to 0
=0: The bridge has not delayed a split request.
a transaction to secondary port due to not enough room within the limit
specified in the split transaction commitment limit field in the downstream
split transaction control register. This bit is RO for forward bridge.
Reset to 0
=1: The bridge has delayed a split request because the bridge cannot forward
=0: No unexpected split completion has been recevied.
=1: An unexpected split completion has been recevied with the
ID equaled to the bridge's secondary port number, device number
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL