PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 43

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.54 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h
6.3.55 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h
Pericom Semiconductor - Confidential
BIT
24:22
31:25
BIT
2:0
7:3
15:8
16
17
18
19
20
21
31:22
FUNCTION
Secondary Clock Frequency
Reserved
FUNCTION
Function Number
Device Number
Bus Number
64-bit Device on Primary
Bus Interface
133MHz Capable
Split Completion Discarded
Unexpected Split
Completion
Split Completion Overrun
Split Request Delayed
Reserved
TYPE
TYPE
RWC
RWC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Function Number; the function number (AD[10:8] of a type-0 configuration
transaction) to which the bridge responds.
Reset to 000
Device Number; the device number (AD[15:11] of a type-0 configuration
transaction) is assigned to the bridge by the connection of system hardware.
Each time the bridge is addressed by a configuration write transaction, the
bridge updates this register with the contents of AD[15:11] of the address
phase of the configuration transaction, regardless of which register in the
bridge is addressed by the transaction. The bridge is addressed by a
configuration write transaction if all of the following are true:
•
•
•
•
Reset to 11111
Bus Number; It is an additional address from which the contents of the
primary bus number register on type-1 configuration space header is read.
The bridge uses the bus number, device number, and function number fields
to create the completer ID when responding with a split completion to a read
of an internal bridge register. These fields are also used for cases when one
interface is in conventional PCI mode and the other is in PCIX mode.
Reset to 11111111
64-bit device.
Reset to 0
133MHz capable on primary interface. This bit is always RO.
Reset to 0 in forward bridge mode or 1 in reverse bridge mode
This bit is always RO.
Reset to 0
=0: No unexpected split completion has been recevied.
=1: An unexpected split completion has been recevied with the request ID
equaled to the bridge's primary port number, device number, and function
number on the bridge primary interface. This bit is RO for reverse bridge.
Reset to 0
This bit is always RO.
Reset to 0
When this bit is set to 1, a split request is delayed because PI7C9X111SL is
not able to forward the split request transaction to its primary bus due to
insufficient room within the limit specified in the split transaction
commitment limit field of the downstream split transaction control register
Reset to 0
0000000000
DESCRIPTION
These bits are only meaningful in forward bridge mode. In reverse bridge
mode, all three bits are set to zero.
000: Conventional PCI mode (minimum clock period not applicable)
001: 66MHz (minimum clock period is 15ns)
010: 100 to 133MHz (minimum clock period is 7.5ns)
011: Reserved
1xx: Reserved
Reset to 000
0000000
The transaction uses a configuration write command.
IDSEL is asserted during the address phase.
AD[1:0] are 00 (type-0 configuration transaction).
AD[10:8] of the configuration address contain the appropriate function
number.
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL