PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 12

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

2
2.1
2.2 PCI EXPRESS SIGNALS
2.3 PCI SIGNALS
Pericom Semiconductor - Confidential
PIN DEFINITIONS
SIGNAL TYPES
NAME
REFCLKP
REFCLKN
RP
RN
TP
TN
PERST_L
NAME
AD [31:0]
CBE_L[3:0]
PAR
FRAME_L
TYPE OF SIGNAL - DESCRIPTIONS
B
I
IU
ID
IOD
OD
O
P
G
Bi-directional
Input
Input with pull-up
Input with pull-down
Bi-directional with open drain output
Open drain output
Output
Power
Ground
PIN ASSIGNMENT
7
9
17
18
14
13
36
PIN ASSIGNMENT
125, 123, 124, 121,
120, 119, 118, 116,
114, 113, 110, 109,
108, 107, 105, 104, 89,
87, 86, 85, 84, 83, 82,
80, 77, 76, 74, 73, 72,
71, 69, 68
115, 102, 90, 79
93
66
TYPE
TYPE
O
B
B
B
B
I
I
I
Page 12 of 78
DESCRIPTION
Reference Clock Inputs: Connect to external 100MHz differential clock. These
signals require AC coupled with 0.1uF capacitors.
PCI Express data inputs: Differential data receiver input signals
PCI Express data outputs: Differential data transmitter output signals
PCI Express Fundamental Reset: PI7C9X111SL uses this reset to initialize the
internal state machines.
DESCRIPTION
Address / Data: Multiplexed address and data bus. Address phase is aligned with
first clock of FRAME_L assertion. Data phase is aligned with IRDY_L or TRDY_L
assertion. Data is transferred on rising edges of CLKOUT[0] when both IRDY_L and
TRDY_L are asserted. During bus idle (both FRAME_L and IRDY_L are de-
asserted), PI7C9X111SL drives AD to a valid logic level when arbiter is parking to
PI7C9X111SL on PCI bus.
Command / Byte Enables (Active LOW): Multiplexed command at address phase
and byte enable at data phase. During address phase, the initiator drives commands on
CBE [3:0] signals to start the transaction. If the command is a write transaction, the
initiator will drive the byte enables during data phase. Otherwise, the target will drive
the byte enables during data phase. During bus idle, PI7C9X111SL drives CBE [3:0]
signals to a valid logic level when arbiter is parking to PI7C9X111SL on PCI bus.
Parity Bit: Parity bit is an even parity (i.e. even number of 1’s), which generates
based on the values of AD [31:0], CBE [3:0]. If PI7C9X111SL is an initiator with a
write transaction, PI7C9X111SL will tri-state PAR. If PI7C9X111SL is a target and
a write transaction, PI7C9X111SL will drive PAR one clock after the address or data
phase. If PI7C9X111SL is a target and a read transaction, PI7C9X111SL will drive
PAR one clock after the address phase and tri-state PAR during data phases. PAR is
tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X111SL
drives PAR to a valid logic level when arbiter is parking to PI7C9X111SL on PCI
bus.
FRAME (Active LOW): Driven by the initiator of a transaction to indicate the
beginning and duration an access. The de-assertion of FRAME_L indicates the final
data phase signaled by the initiator in burst transfers. Before being tri-stated, it is
driven to a de-asserted state for one cycle.
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL