PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 38

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.36 ARBITER PRIORITY REGISTER – OFFSET 48h
6.3.37 RESERVED REGISTERS – OFFSET 4Ch
6.3.38 MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h
6.3.39 MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h
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BIT
20
21
BIT
22
23
24
25
26
27
28
29
30
31
BIT
31:0
BIT
31:0
FUNCTION
GNT_L Output Toggling
Enable
Reserved
FUNCTION
Arbiter Priority 0
Arbiter Priority 1
Arbiter Priority 2
Arbiter Priority 3
Arbiter Priority 4
Reserved
Reserved
Reserved
Reserved
Reserved
FUNCTION
Memory Readsmart Base
Lower 32-bit Register 1
FUNCTION
Memory Readsmart Base
Upper 32-bit register 1
TYPE
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
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DESCRIPTION
0: GNT_L not de-asserted after granted master assert FRAME_L
1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting
FRAME_L
Reset to 0
Reset to 0
DESCRIPTION
0: Low priority request to internal PI7C9X111SL
1: High priority request to internal PI7C9X111SL
Reset to 1
0: Low priority request to master 1
1: High priority request to master 1
Reset to 0
0: Low priority request to master 2
1: High priority request to master 2
Reset to 0
0: Low priority request to master 3
1: High priority request to master 3
Reset to 0
0: Low priority request to master 4
1: High priority request to master 4
Reset to 0
Reset to 0
Reset to 0
Reset to 0
Reset to 0
Reset to 0
DESCRIPTION
Memory Readsmart Base Address 1 in conjunction with Memory Readsmart
Base Lower 32-bit register 1 and Memory Readsmart Range Size register 1,
defines address range 1 in which PCI memory read are allowed
(or not allowed) to use the Readsmart mode which is controlled
Reset to 00000000h
DESCRIPTION
Bit[63:32] of Memory Readsmart Base Address 1
Reset to 00000000h
by bit [7:4] of 40h.
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL