PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 61

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.116 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h
6.3.117 SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h
6.3.118 RESERVED REGISTER – OFFSET 14Ch
6.3.119 VC CAPABILITY ID REGISTER – OFFSET 150h
6.3.120 VC CAPABILITY VERSION REGISTER – OFFSET 150h
Pericom Semiconductor - Confidential
BIT
5
6
7
8
9
10
11
12
13
31:14
BIT
4:0
31:5
BIT
35:0
39:36
43:40
63:44
95:64
127:96
BIT
15:0
FUNCTION
Unexpected Split
Completion Error Severity
Uncorrectable Split
Completion Message Data
Error Severity
Uncorrectable Data Error
Severity
Uncorrectable Attribute
Error Severity
Uncorrectable Address Error
Severity
Delayed Transaction Discard
Timer Expired Severity
PERR_L Assertion Detected
Severity
SERR_L Assertion Detected
Severity
Internal Bridge Error
Severity
Reserved
FUNCTION
Secondary First Error
Pointer
Reserved
FUNCTION
Transaction Attribute
Transaction Command
Lower
Transaction Command
Upper
Reserved
Transaction Address
Transaction Address
FUNCTION
VC Capability ID
TYPE
TYPE
TYPE
TYPE
ROW
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
ROS
ROS
ROS
ROS
ROS
ROS
RO
RO
RO
Page 61 of 78
DESCRIPTION
Reset to 0
Reset to 1
Reset to 0
Reset to 1
Reset to 1
Reset to 0
Reset to 0
Reset to 1
Reset to 0
Reset to 0
DESCRIPTION
Reset to 0
Reset to 0
DESCRIPTION
Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase
Reset to 0
Transaction command lower, CBE [3:0] during first address phase
Reset to 0
Transaction command upper, CBE [3:0] during second address phase of
DAC transaction
Reset to 0
Reset to 0
Transaction address, AD [31:0] during first address phase
Reset to 0
Transaction address, AD [31:0] during second address phase of DAC
transaction
Reset to 0
DESCRIPTION
Reset to 0002h
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL