PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 29

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h
6.3.15 I/O BASE REGISTER – OFFSET 1Ch
6.3.16 I/O LIMIT REGISTER – OFFSET 1Ch
6.3.17 SECONDARY STATUS REGISTER – OFFSET 1Ch
Pericom Semiconductor - Confidential
BIT
23:16
BIT
31:24
BIT
1:0
3:2
7:4
BIT
9:8
11:10
15:12
BIT
20:16
21
22
23
24
FUNCTION
Subordinate Bus Number
FUNCTION
Secondary Latency Timer
FUNCTION
32-bit I/O Addressing
Support
Reserved
I/O Base
FUNCTION
32-bit I/O Addressing
Support
Reserved
I/O Base
FUNCTION
Reserved
66MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
Detected
TYPE
TYPE
TYPE
TYPE
TYPE
RWC
RW /
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 00h
DESCRIPTION
Secondary latency timer in PCI bus
FORWARD BRIDGE –
RW with reset to 00h in PCI mode
REVERSE BRIDGE –
RO with reset to 00h
DESCRIPTION
01: Indicates PI7C9X111SL supports 32-bit I/O addressing
Reset to 01
Reset to 00
Indicates the I/O base (0000_0000h)
Reset to 0000
DESCRIPTION
01: Indicates PI7C9X111SL supports 32-bit I/O addressing
Reset to 01
Reset to 00
Indicates the I/O Limit (0000_0FFFh)
Reset to 0000
DESCRIPTION
Reset to 00000
Indicates PI7C9X111SL is 66MHz capable
Reset to 1
Reset to 0
FORWARD BRIDGE: reset to 1 when secondary bus is in PCI mode
(supports fast back-to-back transactions)
REVERSE BRIDGE: reset to 0 (does not support fast back-to-back
transactions)
This bit is set if its parity error enable bit is set and either of the conditions
occur on the primary:
FORWARD BRIDGE –
•
•
•
REVERSE BRIDGE –
•
•
Reset to 0
Detected parity error when receiving data or split response for read
Observes S_PERR_L asserted when sending data or receiving split
response for write
Receives a split completion message indicating data parity error
occurred for non-posted write
Receives a completion marked poisoned
Poisons a write request
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL