PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 33

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.29 INTERRUPT PIN REGISTER – OFFSET 3Ch
6.3.30 BRIDGE CONTROL REGISTER – OFFSET 3Ch
Pericom Semiconductor - Confidential
BIT
15:8
BIT
16
17
18
19
20
21
22
23
FUNCTION
Interrupt Pin
FUNCTION
Parity Error Response
Enable
SERR_L Enable
ISA Enable
VGA Enable
VGA 16-bit Decode
Master Abort Mode
Secondary Interface Reset
Fast Back-to-Back Enable
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RO
RO
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DESCRIPTION
Designates interrupt pin INTA_L, is used
Reset to 01h
DESCRIPTION
0: Ignore parity errors on the secondary
1: Enable parity error detection on secondary
FORWARD BRIDGE –
Controls the response to uncorrectable address attribute and data errors on the
secondary
REVERSE BRIDGE –
Controls the setting of the master data parity error bit in response to a
received poisoned TLP from the secondary (PCIe link)
Reset to 0
0: Disable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
1: Enable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
Reset to 0 (FORWARD BRIDGE)
RO bit for REVERSE BRIDGE
0: Forward downstream all I/O addresses in the address range defined by the
I/O Base and Limit registers
1: Forward upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
Reset to 0
0: Do not forward VGA compatible memory and I/O addresses from the
primary to secondary, unless they are enabled for forwarding by the defined
I/O and memory address ranges
1: Forward VGA compatible memory and I/O addresses from the primary
and secondary (if the I/O enable and memory enable bits are set),
independent of the ISA enable bit
0: Execute 10-bit address decodes on VGA I/O accesses
1: Execute 16-bit address decode on VGA I/O accesses
Reset to 0
0: Do not report master aborts (return FFFFFFFFh on reads and discards
data on write)
1: Report master abort by signaling target abort if possible or by the
assertion of SERR_L (if enabled).
Reset to 0
0: Do not force the assertion of RESET_L on secondary PCI bus for forward
bridge, or do not generate a hot reset on the PCIe link for reverse bridge
1: Force the assertion of RESET_L on secondary PCI bus for forward
bridge, or generate a hot reset on the PCIe link for reverse bridge
Reset to 0
Fast back-to-back not supported
Reset to 0
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL