PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 34

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.31 PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h
Pericom Semiconductor - Confidential
BIT
24
25
26
27
31:28
BIT
0
1
2
3
5:4
FUNCTION
Primary Master Timeout
Secondary Master Timeout
Master Timeout Status
Discard Timer SERR_L
Enable
Reserved
FUNCTION
Secondary Internal Arbiter’s
PARK Function
Memory Read Prefetching
Dynamic Control Disable
Completion Data Prediction
Control
CFG Type0-to-Type1
conversion Enable
PCI Read Multiple Prefetch
Mode
TYPE
TYPE
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
0: Primary discard timer counts 2
1: Primary discard timer counts 2
FORWARD BRIDGE –
Bit is RO and ignored by the PI7C9X111SL
Reset to 0
0: Secondary discard timer counts 2
1: Secondary discard timer counts 2
REVERSE BRIDGE –
Bit is RO and ignored by PI7C9X111SL
Reset to 0
Bit is set when the discard timer expires and a delayed completion is
discarded at the PCI interface for the forward or reverse bridge
Reset to 0
Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for
forward bridge, or assert P_SERR_L for reverse bridge as a result of the
expiration of the discard timer on the PCI interface.
Reset to 0
Reset to 0000
DESCRIPTION
0: Park to the last master
1: Park to PI7C9X111SL secondary port
Reset to 0
0: Enable memory read prefetching dynamic control for PCI to PCIe read
1: Disable memory read prefetching dynamic control for PCI to PCIe read
Reset to 0
0: Enable completion data prediction for PCI to PCIe read.
1: Disable completion data prediction
Reset to 0
0: CFG Type0-to-Type1 conversion is disabled.
1: CFG Type0-to-Type1 conversion is enabled if the AD[31:28] is all 1s.
bridge will ignore the AD[0] and always treats the cfg transaction as type 1,
other AD bit (except AD[31:28], AD[0]) must meet the Type 1 format
Reset to 0
00: One cache line prefetch if memory read multiple address is in
prefetchable range at the PCI interface
01: Full prefetch if address is in prefetchable range at PCI interface, and the
PI7C9X111SL will keep remaining data after it disconnects the external
master during burst read with read multiple command until the discard timer
expires
10: Full prefetch if address is in prefetchable range at PCI interface
11: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X111SL will keep remaining data after the read multiple is terminated
either by an external master or by the PI7C9X111SL, until the discard time
expires
Reset to 10
15
10
PCI clock cycles
PCI clock cycles
15
10
PCI clock cycles
PCI clock cycles
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL