PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 21

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PI7C9X111SLBFDE

Manufacturer Part Number
PI7C9X111SLBFDE
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C9X111SLBFDE

Lead Free Status / Rohs Status
Compliant

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6
6.1
PI7C9X111SL supports Type-0 and Type-1 configuration space headers and Capability ID of 01h (PCI power
management) to 10h (PCI Express capability structure).
With pin REVRSB = 0, device-port type (bit [7:4]) of capability register will be set to 7h (PCI Express-to-PCI).
When pin REVRSB = 1, device-port type (bit [7:4]) of capability register will be set to 8h (PCI-to-PCI Express
bridge).
PI7C9X111SL supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of
offset 02h).
PI7C9X111SL supports capability pointer with PCI power management (ID=01h), PCI bridge sub-system vendor
ID (ID=0Dh), PCI Express (ID=10h), vital product data (ID=03h), and message signaled interrupt (ID=05h). Slot
identification (ID=04h) is off by default and can be turned on through configuration programming.
Table 6-1 Configuration Register Map (00h – FFh)
Pericom Semiconductor - Confidential
CONFIGURATION REGISTER ACCESS
CONFIGURATION REGISTER MAP
Primary Bus
Configuration Access or
Secondary Bus
Configuration Access
01h - 00h
03h – 02h
05h – 04h
07h – 06h
0Bh – 08h
0Ch
0Dh
0Eh
0Fh
17h – 10h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Fh – 1Eh
21h – 20h
23h – 22h
25h – 24h
27h – 26h
2Bh – 28h
PCI Configuration
Register Name
(type1)
Vendor ID
Device ID
Command Register
Primary Status
Register
Class Code and
Revision ID
Cacheline Size
Register
Primary Latency Timer
Header Type Register
Reserved
Reserved
Primary Bus Number
Register
Secondary Bus
Number Register
Subordinate Bus
Number Register
Secondary Latency
Timer
I/O Base Register
I/O Limit Register
Secondary Status
Register
Memory Base Register
Memory Limit
Register
Prefetchable Memory
Base Register
Prefetchable Memory
Limit Register
Prefetchable Memory
EEPROM
(I2C)
Access
Yes1
Yes1
Yes
Yes
Yes1
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Page 21 of 78
SM Bus
Access
Yes2
Yes2
Yes
Yes
Yes2
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL

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