PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 73

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

13.3 DEVICE ID REGISTER
13.4 BOUNDARY SCAN REGISTER
13.5 JTAG BOUNDARY SCAN REGISTER ORDER
14
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass
instruction is in effect. This allows rapid movement of test data to and from other components on the board. This
path can be selected when no test operation is being performed on the PI7C9X111SL.
This register identifies Pericom as the manufacturer of the device and details the part number and revision number
for the device.
Table 13-2 JTAG device ID register
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by
connected the internal signal of the PI7C9X111SL package pins. The VDD, VSS, and JTAG pins are not in the
boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4
different types of boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into
the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the
mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK.
PI7C9X111SL supports D0, D3-hot, D3-cold Power States. D1 and D2 states are not supported. The PCI Express
Physical Link Layer of the PI7C9X111SL device supports the PCI Express Link Power Management with L0, L0s,
L1, L2/L3 ready and L3 Power States. For the PCI Port of PI7C9X111SL, it supports the standard PCI Power
Management States with B0, B1, B2 and B3.
During D3-hot state, the main power supplies of VDDP, VDDC, and VD33 can be turned off to save power while
keeping the VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary
information to be restored to the full power D0 state. PI7C9X111SL has been designed to have sticky registers that
are powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state
changes. Along with the operating system and application software, PCI devices can achieve optimum power
saving by using PME_L in forward bridge mode. PI7C9X111SL converts PME_L signal information to power
management messages to the upstream switches or root complex. In reverse bridge mode, PI7C9X111SL converts
the power management event messages from PCIe devices to the PME_L signal and continues to request power
management state change to the host bridge.
Pericom Semiconductor - Confidential
POWER MANAGEMENT
Bit
31:28
27:12
11:1
0
Type
RO
RO
RO
RO
Value
01h
E110h
23Fh
1b
Page 73 of 78
Description
Version number
Last 4 digits (hex) of the die part number
Pericom identifier assigned by JEDEC
Fixed bit equal to 1’b1
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL