PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 70

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

11
Pericom Semiconductor - Confidential
HOT PLUG OPERATION
EEPROM Byte
Addresses
2E-30h
31-34h
35-38h
39-3Ch
3D-40h
41-44h
45-48h
49-4Ah
4B-4Ch
4Dh
4E-4Fh
50-51h
52-55h
56-57h
58-5Bh
5C-5Dh
5E-61h
62-63h
64-67h
68-77h
79-7Bh
7C-7Dh
7Eh
7F-82h
83-86h
87-8Ah
8B-8Eh
8F-91h
92h
93h
94h
95-96h
97-98h
99-9Ah
9B-9Eh
9F-A2h
A3-A6h
A7-A8h
A9h
AA-ABh
AC-ADh
AE-AFh
B0-B3h
B4-B6h
B7h
B8-BBh
BC-BFh
C0-C3h
C4-C7h
C8-CBh
CC-CFh
D0-D3h
D4-D5h
D6-D7h
D8-FFh
Cfg Offset
B1-B3h
B4-B7h
BC-BFh
C4-C7h
CC-CFh
D0-D3h
D4-D7h
D9-DAh
F1-F2h
100h
109-10Ah
E0-E1h
E4-E7h
E0-E1h
E4-E7h
E0_E1h
E4-E7h
E0_E1h
E4-E7h
79-7Bh
86h
88-8Bh
8C-8Fh
94-97h
B4-B7h
B8-BAh
C0h
C2-C3h
C8-C9h
3C-3Dh
DC-DFh
F4-F7h
F8-FBh
FC-FDh
7C-7Dh
310-311h
312-313h
04-07h
0C-0Eh
18-1Bh
1C-1Fh
20-23h
24-27h
28-2Bh
2C-2Fh
30-33h
3E-3Fh
Description
PCI Express Capabilities
Device Capabilities
Link Capabilities
Slot Capabilities
XPIP Configuration Register 0
XPIP Configuration Register 1
XPIP Configuration Register 2
VPD Capability
MSI Capability
Advance Error Reporting Capability
Uncorrectable Error Mask register
Extended Cfg Access Address
Extended Cfg Access Data
Extended Cfg Access Address
Extended Cfg Access Data
Extended Cfg Access Address
Extended Cfg Access Data
Extended Cfg Access Address
Extended Cfg Access Data
Reserved
GPIO Data and Control
Reserved
PCIX Bridge status
Upstream Split Transaction
Downstream Split Transaction
PM Control and Status
Device Capabilities
Device Control/Status
Reserved
Link Control/Status
Reserved
Link Control/Status
Slot Control/Status
Interrupt Control
VPD data
Message Address
Message Upper Address
Message Data
Reserved
Sec Interrupt Control
Replay Timer
Ack Latency Timer
Command/Status
Cacheline/Primary Latency Timer/Header Type
Reserved
Bus Number/Secondary Latency Timer
I/O Base/Limit / Secondary Status
Memory Base/Limit
Prefetch Memory Base/Limit
Prefetch Upper 32 Base
Prefetch Upper 32 Limit
I/O Upper 16 Base/Limit
Reserved
Bridge Control
Reserved
Page 70 of 78
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL