LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 112
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LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 17.
C
LPC4350_30_20_10
Objective data sheet
Symbol
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
t
t
t
t
t
CSLAV
CSLOEL
CSLBLSL
OELOEH
am
h(D)
CSHBLSH
CSHOEH
OEHANV
deact
CSLAV
CSLDV
CSLWEL
CSLBLSL
WELWEH
BLSLBLSH
WEHDNV
WEHEOW
BLSHDNV
WEHANV
deact
CSLBLSL
L
= 30 pF, T
Dynamic characteristics: Static external memory interface
Parameter
CS LOW to address valid
time
CS LOW to OE LOW time
CS LOW to BLS LOW time
OE LOW to OE HIGH time
memory access time
data input hold time
CS HIGH to BLS HIGH time PB = 1
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
deactivation time
CS LOW to address valid
time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH time PB = 1
WE HIGH to data invalid
time
WE HIGH to end of write
time
BLS HIGH to data invalid
time
WE HIGH to address invalid
time
deactivation time
CS LOW to BLS LOW
amb
11.8 External memory interface
=
40
[1]
C to 85
[2]
[2]
C, V
DD(REG)(3V3)
Conditions
RD
RD
RD
RD
RD
RD
RD
WR
WR
WR
WR
WR
WR
WR
PB = 1
PB = 1
WR
PB = 1
WR
All information provided in this document is subject to legal disclaimers.
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
; PB = 1
; PB =1
; PB = 1
; PB =1
; PB =1
; PB = 1
; PB = 0;
; PB = 0
Rev. 2.1 — 23 September 2011
= <tbd>.
[1]
[3]
[4]
[5]
Min
<tbd>
<tbd> + T
WAITOEN
<tbd>
(WAITRD
WAITOEN + 1)
T
(WAITRD
WAITOEN +1)
T
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd> + T
(1 + WAITWEN)
<tbd>
(WAITWR
WAITWEN + 1)
T
(WAITWR
WAITWEN + 3)
T
<tbd> + T
<tbd> + T
<tbd>
<tbd> + T
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
<tbd>
<tbd>
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
32-bit ARM Cortex-M4/M0 microcontroller
Typ
<tbd>
<tbd> + T
WAITOEN
<tbd>
(WAITRD
WAITOEN + 1)
T
(WAITRD
WAITOEN +1)
T
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd> + T
(1 + WAITWEN)
<tbd>
(WAITWR
WAITWEN + 1)
T
(WAITWR
WAITWEN + 3)
T
<tbd> + T
<tbd> + T
<tbd>
<tbd> + T
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
LPC4350/30/20/10
<tbd>
<tbd>
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
Max
<tbd>
<tbd> + T
WAITOEN
<tbd>
(WAITRD
WAITOEN + 1)
T
(WAITRD
WAITOEN +1)
T
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd> + T
(1 + WAITWEN)
<tbd>
(WAITWR
WAITWEN + 1)
T
(WAITWR
WAITWEN + 3)
T
<tbd> + T
<tbd> + T
<tbd>
<tbd> + T
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
© NXP B.V. 2011. All rights reserved.
<tbd>
<tbd>
<tbd>
<tbd>
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
112 of 145
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns