LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 81

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.18.6.1 Features
7.18.6 I
7.18.7 C_CAN
Remark: The LPC4350/30/20/10 each contain two I
The I
The I
and one word select signal. The basic I
always the master, and one slave. The I
receive channel, each of which can operate as either a master or a slave.
Remark: The LPC4350/30/20/10 each contain two C_CAN controllers.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of reliability.
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S interface
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
Both I
master or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,
96, 192) kHz.
Support for an audio master clock.
Configurable word select period in master mode (separately for I
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests for each I
These are connected to the GPDMA block.
Controls include reset, stop and mute options separately for I
output.
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S-bus provides a standard communication interface for digital audio applications.
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
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C-bus controllers support multiple address recognition and a bus monitor mode.
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C-bus can be used for test and diagnostic purposes.
S interfaces have separate input/output channels, each of which can operate in
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
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S interface, controlled by programmable buffer levels.
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S-bus connection has one master, which is
S-bus interface provides a separate transmit and
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
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S-bus interfaces.
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S-bus input and I
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S-bus input and
© NXP B.V. 2011. All rights reserved.
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S-bus