LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 61
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LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC4350_30_20_10
Objective data sheet
Symbol
TDI
USB0 pins
USB0_DP
USB0_DM
USB0_VBUS
USB0_ID
USB0_RREF
USB1 pins
USB1_DP
USB1_DM
I
I2C0_SCL
I2C0_SDA
Reset and wake-up pins
RESET
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
ADC pins
ADC0_0/
ADC1_0/DAC
ADC0_1/
ADC1_1
ADC0_2/
ADC1_2
ADC0_3/
ADC1_3
ADC0_4/
ADC1_4
2
C-bus pins
Pin description
J4
F2
G2
F1
H2
H1
F12
G12
L15
L16
D9
A9
A10
C9
D8
E3
C3
A4
B5
C6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
…continued
G3
E1
E2
E3
F1
F3
E9
E10 130 90
D6
E6
B6
A4
-
-
-
A2
A1
B3
A3
-
35
26
28
29
30
32
129 89
132 92
133 93
185 128 91
187 130 93
-
-
-
8
4
206 143 99
200 139 96
199 138 -
26
18
20
21
22
24
-
-
-
6
2
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
16
9
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12
13
15
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63
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-
-
4
1
[3]
[7]
[7]
[7]
[8]
[8]
[9]
[9]
[10]
[10]
[11]
[11]
[11]
[11]
[11]
[8]
[8]
[8]
[8]
[8]
I; PU I
-
-
-
-
-
-
-
I; F
I; F
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I/O USB0 bidirectional D+ line.
I/O USB0 bidirectional D line.
I/O VBUS pin (power on USB cable).
I
I/O USB1 bidirectional D+ line.
I/O USB1 bidirectional D line.
I/O I
I/O I
I
I
I
I
I
I
I
I
I
I
Description
Test Data In for JTAG interface.
Indicates to the transceiver whether connected to an
A-device (LOW) or a B-device (HIGH).
12.0 k (accuracy 1 %) on-board resistor to ground
for current reference.
compliance).
compliance).
External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin
at address 0.
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
ADC input channel 0. Shared between 10-bit ADC0/1
and DAC.
ADC input channel 1. Shared between 10-bit ADC0/1.
ADC input channel 2. Shared between 10-bit ADC0/1.
ADC input channel 3. Shared between 10-bit ADC0/1.
ADC input channel 4. Shared between 10-bit ADC0/1.
2
2
C clock input/output. Open-drain output (for I
C data input/output. Open-drain output (for I
32-bit ARM Cortex-M4/M0 microcontroller
Table
LPC4350/30/20/10
2.
© NXP B.V. 2011. All rights reserved.
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C-bus
C-bus