LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 66
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
Fig 8.
System
AHB MULTILAYER MATRIX
bus
= master-slave connection
CORTEX-M4
TEST/DEBUG
INTERFACE
AHB multilayer matrix master and slave connections
code
bus
ARM
I-
code
7.6.1 Features
bus
D-
7.5 AHB multilayer matrix
7.6 Nested Vectored Interrupt Controller (NVIC)
CORTEX-M0
TEST/DEBUG
INTERFACE
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
•
•
•
•
•
ARM
Controls system exceptions and peripheral interrupts.
In the LPC4350/30/20/10, the Cortex-M4 NVIC supports up to 53 vectored interrupts.
<tbd> programmable interrupt priority levels with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
0
DMA
All information provided in this document is subject to legal disclaimers.
1
Rev. 2.1 — 23 September 2011
ETHERNET
HIGH-SPEED PHY
USB0
USB1
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
LCD
MMC
SD/
masters
128 kB LOCAL SRAM
AHB PERIPHERALS
72 kB LOCAL SRAM
32 kB AHB SRAM
PERIPHERALS
CONTROLLER
© NXP B.V. 2011. All rights reserved.
16 kB + 16 kB
INTERFACES
64 kB ROM
AHB SRAM
EXTERNAL
REGISTER
APB, RTC
MEMORY
DOMAIN
slaves
002aaf873
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