LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 87
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LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
Fig 11. Power domains
USB0_VDDA3V_DRIVER
7.22.8 Reset Generation Unit (RGU)
7.22.9 Power control
USB0_VDDA3V3
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC4350/30/20/10.
The LPC4350/30/20/10 feature several independent power domains to control power to
the core and the peripherals (see
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain which can be powered by a battery supply or
the main regulator. A power selector switch ensures that the RTC block is always powered
on.
The LPC4350/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
VDDREG
RTCX1
RTCX2
VDDIO
VDDA
VSSA
VBAT
VPP
VSS
LPC43xx
All information provided in this document is subject to legal disclaimers.
USB0 POWER DOMAIN
OTP POWER DOMAIN
ALWAYS-ON/RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
SELECTOR
OSCILLATOR
Rev. 2.1 — 23 September 2011
POWER
to I/O pads
32 kHz
to RTC I/O
REGULATOR
pads
Figure
ULTRA LOW-POWER
REGULATOR
OTP
USB0
11). The RTC and its associated peripherals (the
DAC
ADC
BACKUP REGISTERS
REAL-TIME CLOCK
RESET/WAKE-UP
32-bit ARM Cortex-M4/M0 microcontroller
CONTROL
to cores
to memories,
peripherals,
oscillators,
PLLs
LPC4350/30/20/10
to RTC
domain
peripherals
002aag378
RESET
WAKEUP0/1/2/3
ALARM
© NXP B.V. 2011. All rights reserved.
87 of 145
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