LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 117
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
11.10 SD/MMC
Table 20.
T
[1]
[2]
Table 21.
T
Symbol Parameter
t
t
Symbol
f
t
t
t
t
su
h
clk
su(D)
h(D)
d(QV)
h(Q)
amb
amb
Fig 37. Ethernet timing
clk
Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
=
=
40
40
clock duty cycle
set-up time
hold time
Dynamic characteristics: Ethernet
Dynamic characteristics: SD/MMC
C to 85
C to 85
Parameter
clock frequency
data input set-up
time
data input hold time on pins SD_CMD, SD_DATn as
data output valid
delay time
data output hold
time
ENET_RX_CLK
ENET_TX_CLK
ENET_RX_DV
ENET_RX_ER
ENET_RXD[n]
ENET_TX_EN
ENET_TX_ER
ENET_TXD[n]
All information provided in this document is subject to legal disclaimers.
C, V
C, V
Rev. 2.1 — 23 September 2011
DD(REG)(3V3)
DD(REG)(3V3)
Conditions
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
Conditions
on pin SD_CLK; data transfer mode
on pin SD_CLK; identification mode
on pins SD_CMD, SD_DATn as
inputs
inputs
on pins SD_CMD, SD_DATn as
outputs
on pins SD_CMD, SD_DATn as
outputs
= <tbd>.
= 3.0 V to 3.6 V. Values guaranteed by design.
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
t
su
t
h
[1]
[1][2]
[1][2]
Min
<tbd>
<tbd>
<tbd>
002aag210
Min
-
-
6
6
-
3.5
© NXP B.V. 2011. All rights reserved.
Max
<tbd>
-
-
Max
25
25
-
-
23
-
117 of 145
Unit
%
ns
ns
Unit
MHz
MHz
ns
ns
ns
ns
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