LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 64

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
[5]
[6]
[7]
[8]
[9]
[10] Open-drain 5 V tolerant digital I/O pad, compatible with I
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[12] On the TFBGA100 and LQFP208 packages, VPP is internally connected to VDDIO.
[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.
[14] On the TFBGA100 and LQFP100/208 packages, VSS is internally connected to VSSIO.
LPC4350_30_20_10
Objective data sheet
5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC
input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function
and disabling the pull-up resistor through the pin’s SFSP register.
5 V tolerant transparent analog pad.
Transparent analog pad. Not 5 V tolerant.
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
output functionality. When power is switched off, this pin connected to the I
Open-drain configuration applies to all functions on this pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
2
C-bus is floating and does not disturb the I
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2011. All rights reserved.
2
C lines.
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