AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 155

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
21.4.3
21.4.4
21.4.5
21.4.6
21.4.7
21.4.8
Transfer Counter
Reload Registers
Peripheral Selection
Transfer Size
Enabling and Disabling
Interrupts
transfer. The address will be increased by either 1, 2 or 4 depending on the size of the DMA
transfer (Byte, Half-Word or Word). The Memory Address Register can be read at any time dur-
ing transfer.
Each channel has a 16-bit Transfer Counter Register (TCR). This register must be programmed
with the number of transferred to be performed. TCR should contain the number of data items to
be transferred independently of the transfer size. The Transfer Counter Register can be read at
any time during transfer to see the number of remaining transfers.
Both the Memory Address Register and the Transfer Counter Register have a reload register,
respectively Memory Address Reload Register (MARR) and Transfer Counter Reload Register
(TCRR). These registers provide the possibility for the PDCA to work on two memory buffers for
each channel. When one buffer has completed, MAR and TCR will be reloaded with the values
in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero
while TCRR holds a non-zero value.
The Peripheral Select Register decides which peripheral should be connected to the PDCA
channel. Configuring PSR will both select the direction of the transfer (memory to peripheral or
peripheral to memory), which handshake interface to use, and the address of the peripheral
holding register.
The transfer size can be set individually for each channel to be either Byte, Half-Word or Word
(8-bit, 16-bit or 32-bit respectively). Transfer size is set by programming the SIZE bit-field in the
Mode Register (MR).
Each DMA channel is enabled by writing ‘1’ to the Transfer Enable bit (TEN) in the Control Reg-
ister (CR) and disabled by writing ‘1’ to the Transfer Disable bit (TDIS). The current status can
be read from the Status Register (SR).
Interrupts can be enabled by writing to the Interrupt Enable Register (IER) and disabled by writ-
ing to Interrupt Disable Register (IDR). The Interrupt Mask Register (IMR) can be read to see
whether an interrupt is enabled or not. The current status of an interrupt source can be read
through the Interrupt Status Register (ISR).
The PDCA has three interrupt sources:
• Reload Counter Zero - The Transfer Counter Reload Register is zero.
• Transfer Finished - Both the Transfer Counter Register and Transfer Counter Reload Register
• Transfer Error - An error has occurred in accessing memory.
are zero.
AT32UC3A
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