AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 654

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
31.7
Timer Counter (TC) User Interface
Table 31-3.
BCR (Block Control Register) and BMR (Block Mode Register) control the whole TC block. TC
channels are controlled by the registers listed in
registers in
Table 31-4
Table 31-4.
Notes:
Offset
Offset
0xC0
0xC4
0x00
0x40
0x80
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
1. Read-only if WAVE = 0
.
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
Channel Control Register
Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Table 31-4
TC Global Memory Map
TC Channel Memory Map
is in relation to the offset of the corresponding channel as mentioned in
Name
CMR
CCR
IMR
IDR
Name
IER
RC
CV
RA
RB
SR
BMR
BCR
Table 31-4
. The offset of each of the channel
See
See
See
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read/Write
Write-only
Access
Access
Table 31-4
Table 31-4
Table 31-4
(1)
(1)
AT32UC3A
Reset Value
Reset Value
–
0
–
–
0
0
0
0
0
–
–
0
–
0
654