AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 344

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• CLKO: Clock Output Select
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• MSBF/CPOL: Bit Order or SPI Clock Polarity
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
• CHMODE: Channel Mode
• NBSTOP: Number of Stop Bits
0
0
1
1
0
– If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
– If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CHMODE
NBSTOP
0
1
0
1
0
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input..
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC = 0)
1 stop bit
Synchronous (SYNC = 1)
1 stop bit
AT32UC3A
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