AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 177

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Table 22-2.
22.5.1
Offset
0xA0
0xA4
0xA8
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
0xE0-
0xFF
Access Types
Register
Interrupt Mode Register 0
Interrupt Mode Register 0
Interrupt Mode Register 0
Interrupt Mode Register 0
Interrupt Mode Register 1
Interrupt Mode Register 1
Interrupt Mode Register 1
Interrupt Mode Register 1
Glitch Filter Enable Register
Glitch Filter Enable Register
Glitch Filter Enable Register
Glitch Filter Enable Register
Interrupt Flag Register
Interrupt Flag Register
Interrupt Flag Register
Interrupt Flag Register
RESERVED
GPIO Register Map
Each configuration register can be accessed in four different ways. The first address location
can be used to write the register directly. This address can also be used to read the register
value. The following addresses facilitate three different types of write access to the register. Per-
forming a “set” access, all bits written to ‘1’ will be set. Bits written to ‘0’ will be unchanged by the
operation. Performing a “clear” access, all bits written to ‘1’ will be cleared. Bits written to ‘0’ will
be unchanged by the operation. Finally, a toggle access will toggle the value of all bits written to
‘1’. Again all bits written to ‘0’ remain unchanged. Note that for some registers (e.g. IFR), not all
access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
Function
Read/Write
Set
Clear
Toggle
Read/Write
Set
Clear
Toggle
Read/Write
Set
Clear
Toggle
Read
-
Clear
-
-
Name
IMR0
IMR0S
IMR0C
IMR0T
IMR1
IMR1S
IMR1C
IMR1T
GFER
GFERS
GFERC
GFERT
IFR
-
IFRC
-
-
Access
Read/Write
Write-Only
Write-Only
Write-Only
Read/Write
Read/Write
Write-Only
Write-Only
Write-Only
Write-Only
Write-Only
Write-Only
Read-Only
-
Write-Only
-
-
Reset value
0x00000000
0x00000000
1b for each
implemented
GPIO pin in port
0x00000000
AT32UC3A
177