AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 76

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
13.6.7
Name:
Access Type:
•
•
•
•
•
•
•
•
BODDET: Brown out detection
OSC32RDY: 32 KHz oscillator Ready
OSC1RDY: Oscillator 1 Ready
OSC0RDY: Oscillator 0 Ready
MSKRDY: Mask Ready
CKRDY: Clock Ready
LOCK1: PLL1 locked
LOCK0: PLL0 locked
OSC0RDY
31
23
15
7
-
-
-
Set to 1 when 0 to 1 transition on POSCSR:BODDET bit is detected:
BOD reference value.
Set to 1 when 0 to 1 transition on the POSCSR:OSC32RDY bit is detected:
used as clock source.
Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:
clock source.
Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:
clock source.
Set to 1 when 0 to 1 transition on the POSCSR:MSKRDY bit is detected:
(CPU/HSB/PBA/PBB)_MASK registers.
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing ICR:CKRDY to 1 has no effect.
Set to 1 when 0 to 1 transition on the POSCSR:LOCK1 bit is detected:
source.
Set to 1 when 0 to 1 transition on the POSCSR:LOCK0 bit is detected:
source.
Interrupt Enable/Disable/Mask/Status/Clear
MSKRDY
30
22
14
6
IER/IDR/IMR/ISR/ICR
IER/IDR/ICR: Write-only
IMR/ISR: Read-only
-
-
-
CKRDY
29
21
13
5
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
BOD has detected that power supply is going below
PLL 1 is locked and ready to be selected as clock
PLL 0 is locked and ready to be selected as clock
Clocks are now masked according to the
Oscillator 1 is stable and ready to be used as
Oscillator 1 is stable and ready to be used as
The 32 KHz oscillator is stable and ready to be
26
18
10
2
-
-
-
-
OSC32RDY
LOCK1
25
17
9
1
-
-
AT32UC3A
OSC1RDY
BODDET
LOCK0
24
16
8
0
-
76