AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 750

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
36.8.5
36.8.6
36.9
36.9.1
Private JTAG Instructions
CLAMP
BYPASS
Notation
This instruction selects the Bypass register as Data Register. The device output pins are driven
from the Boundary-Scan Chain.
The active states are:
The active states are:
The AVR32 defines a number of private JTAG instructions. Each instruction is briefly described
in text, with details following in table form.
Table 36-4 on page 751
corresponds to one bit, and eight bits are grouped together for readability. The rightmost bit is
always shifted first, and the leftmost bit shifted last. The symbols used are shown in
Table 36-3.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
JTAG instruction selecting the 1-bit Bypass Register for Data Register.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to internal logic inputs.
• Capture-DR: Loads a logic ‘0’ into the Bypass Register.
• Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
• Capture-DR: Loads a logic ‘0’ into the Bypass Register.
• Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
Symbol
0
1
a
b
d
e
p
s
x
r
Description
Constant low value - always reads as zero.
Constant high value - always reads as one.
An address bit - always scanned with the least significant bit first
A busy bit. Reads as one if the SAB was busy, or zero if it was not. See
details on how the busy reporting works.
A data bit - always scanned with the least significant bit first.
An error bit. Reads as one if an error occurred, or zero if not. See
on how the error reporting works.
The chip protected bit. Some devices may be set in a protected state where access to chip
internals are severely restricted. See the documentation for the specific device for details.
On devices without this possibility, this bit always reads as zero.
A direction bit. Set to one to request a read, set to zero to request a write.
A size bit. The size encoding is described where used.
A don’t care bit. Any value can be shifted in, and output data should be ignored.
Symbol description
shows bit patterns to be shifted in a format like " peb01 ". Each character
Section 36.6.4.2
AT32UC3A
Section 36.6.4.1
Table
for details
36-3.
for
750