AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 617

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.8.3.13
Offset:
Register Name:
Access Type:
Reset Value:
• RXINI: Received IN Data Interrupt Flag
Set by hardware when a new USB message is stored in the current bank of the Pipe. This triggers an interrupt if the RXINE
bit is set. Shall be cleared by software (by setting the RXINIC bit).
• TXOUTI: Transmitted OUT Data Interrupt Flag
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is set.
Shall be cleared by software (by setting the TXOUTIC bit).
• TXSTPI: Transmitted SETUP Interrupt Flag
For Control endpoints. Set by hardware when the current SETUP bank is free and can be filled. This triggers an interrupt if
the TXSTPE bit is set. Shall be cleared by software (by setting the TXSTPIC bit).
• UNDERFI: Underflow Interrupt Flag
Set by hardware when a transaction underflow occurs in the current isochronous or interrupt pipe. (the pipe can’t send the
OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be send instead of. This
triggers an interrupt if the UNDERFLE bit is set. Shall be cleared by software (by setting the UNDERFIC bit).
• PERRI: Pipe Error Interrupt Flag
Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt if the PERRE bit is set.
Refers to the UPERRX register to determine the source of the error. Automatically cleared by hardware when the error
source bit is cleared.
• NAKEDI: NAKed Interrupt Flag
Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers an interrupt if the NAKEDE
bit is set. Shall be cleared by software (by setting the NAKEDIC bit).
PACKETI
SHORT
31
23
15
–
0
0
7
0
r
CURRBK
USB Pipe X Status Register (UPSTAX)
r
RXSTALLDI/
CRCERRI
30
22
14
0
0
0
6
0
r
PBYCT
r
OVERFI
29
21
13
0
0
0
5
0
r
0x0530 + X . 0x04
UPSTAX, X in [0..6]
Read-Only
0x00000000
NBUSYBK
r
NAKEDI
28
20
12
0
0
0
4
0
r
PBYCT
PERRI
27
19
11
0
–
–
3
0
r
r
UNDERFI
TXSTPI/
CFGOK
26
18
10
0
0
–
2
0
r
r
TXOUTI
25
17
0
–
9
0
1
0
r
AT32UC3A
DTSEQ
r
RWALL
RXINI
24
16
0
0
8
0
0
0
r
r
617