AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 748

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
36.7
Table 36-2.
36.7.1
Instruction
OPCODE
Others
0x0C
0x0F
0x1C
0x1F
0x01
0x02
0x03
0x04
0x06
0x10
0x11
0x12
0x13
0x14
0x15
0x17
JTAG Instruction Summary
Security restrictions
JTAG Instruction Summary
SAMPLE_PRELOAD
EXTEST
INTEST
CLAMP
NEXUS_ACCESS
MEMORY_SIZED_ACCESS
SYNC
Instruction
IDCODE
AVR_RESET
CHIP_ERASE
MEMORY_WORD_ACCESS
MEMORY_BLOCK_ACCESS
CANCEL_ACCESS
MEMORY_SERVICE
HALT
BYPASS
N/A
Memory can be written while the CPU is executing, which can be utilized for debug purposes.
When downloading a new program, the JTAG HALT instruction should be used to freeze the
CPU, to prevent partially downloaded code from being executed.
The implemented JTAG instructions in the AVR32 are shown in the table below.
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
Description
Select the 32-bit ID register as data register.
Take a snapshot of external pin values without affecting system
operation.
Select boundary scan chain as data register for testing circuitry
external to the device.
Select boundary scan chain for internal testing of the device.
Bypass device through Bypass register, while driving outputs from
boundary scan register.
Apply or remove a static reset to the device
Erase the device
Select the SAB Address and Data registers as data register for the
TAP. The registers are accessed in Nexus mode.
Select the SAB Address and Data registers as data register for the
TAP.
Select the SAB Data register as data register for the TAP. The
address is auto-incremented.
Cancel an ongoing Nexus or Memory access.
Select the SAB Address and Data registers as data register for the
TAP. The registers are accessed in Memory Service mode.
Select the SAB Address and Data registers as data register for the
TAP.
Synchronization counter
Halt the CPU for safe programming.
Bypass this device through the bypass register.
Acts as BYPASS
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