AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 703

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
33.6.4
Figure 33-2. EOCx and DRDY Flag Behavior
CHx(CHSR)
DRDY(SR)
EOCx(SR)
Conversion Results
With START=1
Write CR
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (CDR) of the current channel and in the ADC Last Converted Data Register (LCDR).
The channel EOC bit in the Status Register (SR) is set and the DRDY is set. In the case of a
connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC
and DRDY can trigger an interrupt.
Reading one of the CDR registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit corresponding to the last converted channel.
Conversion Time
Read CDRx
With START=1
Write CR
Conversion Time
AT32UC3A
Read LCDR
703