TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 118

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

P1
(0004H)
P1DR
(0081H)
P1CR
(0006H)
P1FC
(0007H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
(Note2)
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for P1CR, P1FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
P17C
P17D
P17
−
7
7
7
7
1
0
−
P16C
P16D
P16
−
6
6
6
6
1
0
−
Data from external port (Output latch register is cleared to “0”)
Figure 3.7.2 Register for Port1
Input/Output buffer drive register for standby mode
Port 1 Function register
Port 1 Control register
P15C
P15D
P15
Port 1 Drive register
0
−
5
5
5
5
1
−
92CF26A-116
Port 1 register
0: Input 1: Output
P14C
P14D
P14
4
4
0
−
4
4
−
1
R/W
R/W
W
−
P13C
P13D
P13
3
3
3
−
3
−
0
1
P12C
P12D
P12
2
2
2
−
2
0
1
−
P11C
P11D
P11
1
1
1
0
−
1
−
1
0: Port
1:Data bus
(D8 to D15)
TMP92CF26A
P10C
P10D
P10
P1F
0/1
W
0
0
0
0
−
−
0
1
−
2009-06-25