TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 160

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PP
(0060H)
PPCR
(0062H)
PPFC
(0063H)
PPDR
(0098H)
PP3 setting
<PP3F>
<PP3C>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for the registers PPCR, PPFC.
Note2: When setting PP5, PP4, PP3 pins to INT7,INT6,INT5 input, set PPDR<PP5D:3D> to “0000” (prohibit input),
INT5 input
Input port
0
and when driving PP5,PP4,PP3 pins to “0”, execute HALT instruction. This setting generates INT7, INT6, and
INT5 inside. If don’t using external interrupt in HALT condition, set like an interrupt don’t generated.
0:Port
1:TB1OUT0
PP7D
PP7F
PP7
Output port
7
7
7
7
TA7OUT
0
−
0
−
1
−
output
1
0:Port
1:TB0OUT0
PP6D
PP6F
PP6
Figure 3.7.48 Register for Port P
6
6
6
6
0
−
1
−
0
−
Input/Output buffer drive register for standby mode
PP2 setting
PP5 setting
<PP2F>
<PP5F>
<PP2C>
<PP5C>
Data from external port (Output latch register is cleared to “0”)
0
1
0
1
Port P function register
Port P control register
PP5C
PP5F
PP5D
PP5
Port P drive register
5
5
5
5
0
−
0
−
1
−
92CF26A-158
Port P register
INT7 input
Reserved
Input port
Input port
0
0
PP4C
PP4F
PP4D
R/W
PP4
R/W
W
4
4
4
0
0
−
4
−
1
−
Refer to following table
Output port
Output port
0: Input 1: Output
TA5OUT
TB1IN0
output
input
1
1
PP3C
PP3F
PP3D
PP3
3
W
3
3
−
3
0
−
0
−
1
−
PP4 setting
<PP1F>
<PP4F>
PP1 setting
<PP1C>
<PP4C>
PP2F
PP2C
PP2D
PP2
0
1
0
1
2
2
2
0
−
2
0
−
1
−
INT6 input
Input port
Reserved
Input port
PP1C
PP1F
PP1D
0
0
PP1
1
1
1
0
−
0
−
1
1
−
TB0IN0 input
Output port
Output port
TA3OUT
output
TMP92CF26A
1
1
0
0
0
0
2009-06-25