TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 601

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TMP92CF26A
3. Disabling the clock
A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in
order to prevent malfunction caused by the Carry hold circuit. While the clock is
prohibited, the Carry hold circuit holds a one sec. carry signal from a divider.
When the clock becomes enabled, the carry signal is output to the clock, the time
is revised and operation continues. However, the clock is delayed when
clock-disabled state continues for one second or more. Note that at this time
system power is down while the clock is disabled. In this case the clock is stopped
and clock is delayed.
Start
Disable the clock
Write the clock data
Enable the clock
End
Figure 3.21.3 Flowchart of Clock disable
2009-06-25
92CF26A-599