TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 125

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Port read data
Port read data
NDRE
WRLL
3.7.5
,
,
NDWE
WRLU
individually set as either inputs or outputs by control register P7CR and function register
P7FC.
function as interface-pins for external memory.
to the following function pins:
Port 7 (P70 to P76)
Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be
In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also
A reset initializes P70 pin to output port mode, and P71 to P76 pins to input port mode.
Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7
RD
AM1
0
0
1
1
P7CR register
P7FC register
P7FC register
P7 register
P7 register
AM0
0
1
0
1
Selector
0
1
Function Setting after reset is released
Initial setting of P70 pin
S
Figure 3.7.9 Port7
92CF26A-123
Selector
S 1
Don’t use this setting
Don’t use this setting
0
Output port (P70)
Selector
0
1
S
Selector
RD pin
0
1
S
TMP92CF26A
2009-06-25
P71 (
P72 (
P70 (
WRLU
WRLL
RD
)
,
,
NDWE
NDRE
)
)