TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 320

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SCLK0
SCLK0
RXD0
3.14.1
φT0
f
IO
SC0MOD0
<RXE>
φT0
φT2
φT8
φT32
Block Diagram
RXDCLK
Serial clock generation circuit
I/O interface mode
RB8
BR0CR<BR0CK1:0>
2
Receive buffer 1 (Shift register)
φT2
Receive counter
(UART only ÷ 16)
4 8 16 32
Prescaler
Receive buffer 2 (SC0BUF)
Receive
control
Baud rate generator
φT8
<BR0S3:0>
BR0CR
φT32
<BR0ADDE>
64
BR0CR
SC0MOD0
<WU>
<BR0K3:0>
BR0ADD
Figure 3.14.2 Block Diagram
<OERR> <PERR> <FERR>
92CF26A-318
÷2
<PE>
interrupt control
Serial channel
Internal data bus
Parity control
Error flag
TA0TRG
(from TMRA0)
SC0CR
SC0CR
SC0MOD0
<SC1:0>
SC0CR
<IOC>
<EVEN>
I/O interface mode
UART
mode
SC0MOD0
<SM1:0>
TXDCLK
TB8
(UART only ÷ 16)
Transmission
Transmision
Transmission buffer (SC0BUF)
SIOCLK
counter
control
SC0MOD0
<CTSE>
TMP92CF26A
2009-06-25
INT request
INTRX0
INTTX0
CTS0
TXD0