TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 543

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCP0 signal
LD23-LD0 signal
LDINV signal
LLOAD signal
LLOAD signal LCDLDDLY<PDT> = 1
LD23-LD0 signal
LVSYNC signal
LHSYNC signal
LLOAD signal
(3) LLOAD Signal
The period of the LLOAD signal synchronizes to one line of display. It is defined as an
integral multiple of the reference clock LCP0.
the time whereas the LLOAD signal is output only at valid data lines (commons).
inserted in the LLOAD signal through the LCDLDDLY register, data output is also
delayed.
LLOAD signal.
Therefore, even if the delay time is set to “0” with LCDLDDLY<PDT>=0, the LLOAD signal
is output with a delay of one LCP0 clock. Be careful about this point.
The LLOAD signal is used to control the timing for the LCD driver to receive display data.
The LHSYNC signal and LLOAD signal differs in that the LHSYNC signal is output all
Display data is output in synchronization with the LLOAD signal. Therefore, if a delay is
Also note that when LCDLDDLY<PDT>=1, data is output one LCP0 clock later than the
LCDLDDLY<PDT>=0: Data is output in synchronization with the LLOAD signal.
LCDLDDLY<PDT>=1: Data is output one LCP0 clock later than the LLOAD signal.
The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1.
Front dummy LHSYNC
(Vertical front porch)
92CF26A-541
Refresh rate
LLOAD: Common size
(Valid data)
Back dummy LHSYNC
(Vertical back porch)
TMP92CF26A
2009-06-25