TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 640

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

supplied to all the blocks in the TMP92CF26A.
on-chip circuit blocks excluding the CPU, part of on-chip RAM, AD converter and RTC. This
leads to a reduction of the leakage current. In the Power Cut mode, power is supplied only to the
followings: I/O (including the AD pins), TSI circuit, 16 Kbytes of on-chip RAM, low-frequency
oscillation circuit, RTC and PMC.
TMP92CF26A
Figure 3.25.2 shows the examples of the PMC application circuit.
In normal mode, the power management pin (PWE) goes high, which allows the power to be
In the Power Cut mode, the PWE pin goes low, which allows the power to be removed from the
ADC
AVSS
AVCC
Figure 3.25.2 Application Circuit Examples of the PMC
DVCC-1C
DVSS-1C
Other Logic
High_OSC
SW en
CPU
DVCC-1A
SW en
DVSS-COM
92CF26A-638
LOW_OSC
XT1
RAM16kB
DVCC-1B DVCC-3A, 3B
Regulator
PMC
RTC
1.5 V
XT2
Regulator
SW en
3.3 V
I/O
Delay Circuit
Power management
signal (PWE)
RESET
External interrupts
INT0-INT7
(INT4 can be programmed as
TSI.)
INTKEY
S 1
0
Reset Circuit
Power-On
TMP92CF26A
2009-06-25
Main
Power