TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 513

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

When I2SnCTL<WLVLn> = “0”
When I2SnCTL<WLVLn> = “1”
I2SnBUF register
I2SnBUF register
Output order
Output order
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
Note: In case of using monaural setting, and change right / left: I2SnCTL<WLVLn>, data output order change off 1'st
data and 2'nd data.
The following shows how written data is output under various conditions.
4’th Data
3’rd Data
2’nd Data
1’st Data
2’nd Data
1’st Data
31
15
31
15
1’st Data
2’nd Data
30
14
30
14
29
13
29
13
28
12
28
12
27
27
11
11
92CF26A-511
26
10
26
10
4’th Data
3’rd Data
2’nd Data
25
25
1’st Data
9
9
24
24
8
8
3’rd Data
4’th Data
23
23
1’st Data
2’nd Data
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
TMP92CF26A
18
18
2
2
2009-06-25
1’st Data
2’nd Data
4’th Data
17
17
3’rd Data
1
1
2’nd Data
1’st Data
2’nd Data
1’st Data
16
16
0
0