TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 39

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

releasing Halt
(3) Operation
releasing Halt
Interrupt for
Interrupt for
D0~D31
A0~A23
Figure 3.3.7 Timing chart for IDLE2 Mode Halt state cleared by interrupt
Figure 3.3.8 Timing chart for IDLE1 Mode Halt state cleared by interrupt
a. IDLE2 Mode
b. IDLE1 Mode
D0~D31
A0~A23
WR
RD
WR
RD
X1
IDLE2 Setting Register, can take place. Instruction execution by the CPU stops.
Mode Halt state by an interrupt.
operate. The system clock stops.
system clock; however, clearance of the Halt state (i.e. restart of operation) is
synchronous with it.
an interrupt.
X1
In IDLE2 Mode, only specific internal I/O operations, as designated by the
Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2
In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to
In the Halt state, the interrupt request is sampled asynchronously with the
Figure 3.3.8 illustrates the timing for clearance of the IDLE1 Mode Halt state by
Data
Data
92CF26A-37
IDLE2
mode
IDLE1
mode
TMP92CF26A
2009-06-25
Data
Data