TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 225

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDCMM
(0253H)
SDBLS
(0254H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note 1: <SCMM2:0> is automatically cleared to “000” after the specified command is issued. Before writing the next
Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed.
command, make sure that <SCMM2:0> is “000”. In the case of the Self Refresh Entry command, however,
<SCMM2:0> is not cleared to “000” by execution of this command. Thus, this register can be used as a flag for
checking whether or not Self Refresh is being performed.
7
7
SDRAM HDMA Burst Length Select Register
6
6
Figure 3.10.1 Control Registers
SDRAM Command Register
For
HDMA5
SDBL5
5
5
0
92CF26A-223
For
HDMA4
SDBL4
4
4
0
1: Full page read / Burst write
0: 1 Word read / Single write
For
HDMA3
SDBLS
HDMA burst length
3
3
0
R/W
Command issue (Note 1) (Note 2)
000: Don’t care
001: Initialization sequence
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
For
HDMA2
SCMM2
SDBL2
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
2
2
0
0
For
HDMA1
SCMM1
SDBL1
R/W
1
1
0
0
TMP92CF26A
For
HDMA0
2009-06-25
SCMM0
SDBL0
0
0
0
0