TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 292

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(3) 8-bit PPG (Programmable pulse generation) output mode
Value of up counter
(UC1, UC0)
TMRA0 comparator
match detect signal
Interrupt INTTA1
Timer output TA1OUT
TMRA1 comparator
match detect signal
Interrupt INTTA0
matches TA0REG, though the up counter UC0 is not cleared.
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparator
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
The output pulses may be active-low or active-high. In this mode TMRA1 cannot be
used.
<TA1FFC1:0> = “10”
<TA1FFC1:0> = “01”
Example: <TA1FFC1:0> = “01”
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interrupt INTTA1)
TA1OUT
The comparator match signal is output from TMRA0 each time the up counter UC0
In the case of the TMRA1 comparator, the match detect signal is output on each
Square wave pulses can be generated at any frequency and duty ratio by TMRA0.
TMRA0 outputs pulses on the TA1OUT pin.
Figure 3.12.19 Timer Output by 16-Bit Timer Mode
Figure 3.12.20 8-Bit PPG Output Waveforms
0080H
92CF26A-290
0180H
t
t
H
L
t
t
TA0REG
0280H
t
t
H
L
TA1REG
0380H
0480H
Inversion
TMP92CF26A
0080H
2009-06-25