TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 516

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(3) Considerations for using the I
1) INTI2Sn generation timing
2) I2SnCTL<TXEn>
3) I2SnCTL<CNTEn>
64 bytes of empty space in the FIFO (after 61- 64th byte has been transferred to
the shift register). The other is when the FIFO becomes completely empty (after
125-128th byte has been transferred to the shift register). Therefore, INTI2Sn
indicates that there are 64 bytes or 128 bytes of empty space in the FIFO,
enabling the next data to be written.
bytes of data, I
bytes of data in the FIFO. It is also possible to check the FIFO state by using the
I2SnCTL<TEMPn> flag.
to “1”, transmission is continued automatically as long as the FIFO contains the
data to be transmitted. While <TXE> is set to “1” (transmission in progress), the
other bits in the I2SnCTL register must not be changed.
I2SnCTL<TEMPn> flag. Then, after waiting for two periods of the I2SWS signal
(after all the data has been transmitted), set <TXEn> to “0”. In case monaural
setting, make sure that the FIFO is empty by checking the I2SnCTL<TEMPn>
flag. Then, after waiting for four periods of the I2SWS signal (after all the data
has been transmitted), set <TXEn> to “0”.
stopped immediately. At the same time, the read and write pointers of the FIFO,
the data in the output shift register and the clock generator are all cleared.
(However, when I2SnCTL<CNTEn>=1, the clock generator is not cleared. To clear
the clock generator, I2SnCTL<CNTEn> must be set to “0”). Therefore, if
transmission is stopped and then resumed, no data will be output.
rising edge is selected and at High level when the falling edge is selected.
counter) for generating the I2SnCKO and I2SnWSOsignals.
stops the counters. Normally, I
I2SnCTL<TXEn> and <CNTEn> to “1”. When transmission is stopped by setting
I2SnCTL<TXEn> to “0” with I2SnCTL<CNTEn>=1, the clock generator is not
cleared. To clear the clock generator, I2SnCTL<CNTEn> must be set to “0”.
Every 4bytes data trance from FIFO buffer to shift register per one time.
An INTI2Sn interrupt is generated under two conditions. One is when there are
The FIFO must be written in units of 64 bytes. Since the FIFO can contain 128
Transmission is started by setting I2SnCTL <TXEn> to “1”. Once <TXEn> is set
To stop transmission, make sure that the FIFO is empty by checking the
If <TXEn> is set to “0” while data is being transmitted, the transmission is
The WS signal stops at Low level and the CK signal stops at Low level when the
I2SnCTL<CNTEn> is used to control the clock generator (8-bit counter, 6-bit
Setting I2SnCTL<CNTEn> to “1” starts the counters, and setting this bit to “0”
2
S output can be performed continuously as long as there are 64
92CF26A-514
2
S unit
2
S data transmission is executed by setting both
TMP92CF26A
2009-06-25