TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 180

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
3.8
3.8.1
Memory Controller (MEMC)
programmable address spaces:
(1) Four programmable address spaces
(2) Memory specification
(3) Data bus width specification
(4) Wait control
The TMP92CF26A has a memory controller with the following features to control four
Functional Overview
spaces (CS0 to CS3 spaces).
selected address spaces.
wait state bits of the control register and the
of a read cycle and that of a write cycle can be specified individually. The number of wait
states can be selected from the following 15 options:
* SRAM or ROM: All CS spaces (CS0 to CS3) can be assigned.
* SDRAM: Either the CS1 or CS2 space can be assigned.
* Page-ROM: Only the CS2 space can be assigned.
* NAND-Flash: It is not required to setup the CS lines. However, when using
The MEMC can specify a start address and a block size for each of the four memory
The MEMC can specify the type of memory, SRAM, ROM, SDRAM to associate with the
The data bus width is selectable from 8 and 16 bits for the respective chip select spaces.
The number of wait states to be inserted into an external bus cycle is determined by the
0 to 10 wait states, 12 wait states,
16 wait states, 20 wait states
4+N wait states (controlled by the WAIT pin)
NAND-Flash, set the BROMCR<CSDIS> bit to 1 to assign an
external area to avoid data conflicts with CS spaces.
92CF26A-178
WAIT
input pin. The number of wait states
TMP92CF26A
2009-06-25

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