TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 544

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDCTL0
(0285H)
LCDPRVSP
(028EH)
Signal Name
LCP0
LLOAD signal
Note: The vertical back porch must be set to “1” or longer in all the cases (STN/TFT).
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
LCDPRVSP<PLV6:0>. This delay time can be set in a range of 0 to 127 pulses of the LCP0
clock.
LCDCTL0<LCP0OC> setting, as shown below.
The number of pulses in the front dummy LHSYNC (vertical front porch) is specified by
Front dummy LHSYNC = <PLV6:0>
The back dummy LHSYNC (vertical back porch) is defined as follows:
(<LVP9:0> + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC: <PLV6:0>)
The enable width of the LLOAD signal is determined depending on the
LCDCTL0<LCP0OC> = 0
LCDCTL0<LCP0OC> = 1
PIP
function
0:Disable
1:Enable
PIPE
7
7
0
Segment
data
0: Normal
1: Always
output “0”
PLV6
LCD LVSYNC Pre Pulse Register
High width setting
LCP0 clock = 1, 2, 3 … 1023 pulses (<PDT>=0) / 1024 pulses (<PDT>=1)
R/W
6
0
ALL0
0
6
LCD Control 0 Register
92CF26A-542
Frame
divide
setting
0: Disable
1: Enable
PLV5
: Output at setting value in (LCDDLW) <LDW9:0>
: Output at valid data
FRMON
5
0
0
5
Always
write “0”
Front dummy LVSYNC (bits 6-0)
PLV4
4
0
R/W
4
−
0
PLV3
W
3
0
3
FR signal
LCP0/Line
selection
0:Line
1:LCP0
PLV2
2
0
DLS
2
0
LCP0(Note
0: Always
1: At valid
LLOAD
0: At setting
1: At valid
PLV1
width
LCP0OC
output
data only
in register
data only
1
0
R/W
1
0
TMP92CF26A
2009-06-25
LCDC
operation
0: Stop
1: Start
PLV0
START
0
0
0
0