S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 189

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
13704CFG Configuration Program
Issue Date: 02/03/11
The S1D13704 uses one clock input known as CLKI. The pixel clock (PCLK) and the
memory clock (MCLK) are both derived directly from CLKI.
CLKI
PCLK
MCLK
CLKI/2
Source
Divide
Timing
Source
Divide
Timing
This setting establishes the frequency of CLKI. CLKI is
the source for both PCLK and MCLK.
The CLKI frequency must be selected from the drop
down list or by entering the desired frequency in MHz.
The CLKI frequency used for configuration is displayed
in blue in the Actual section.
Selecting this box divides the input clock, CLKI, in half
for internal S1D13704 operations.
These settings confirm the signal source and input clock
divisor for the pixel clock (PCLK).
The PCLK source is CLKI.
The divide ratio for the clock source signal is 1:1.
This field shows the actual PCLK used by the configu-
ration process.
These settings confirm the signal source and input clock
divisor for the memory clock (MCLK).
The MCLK source is CLKI.
The divide ratio for the clock source signal is 1:1.
This field shows the actual MCLK frequency used by
the configuration process.
X26A-B-001-03
S1D13704
Page 11